公开(公告)号：US4681657A

公开(公告)日：1987-07-21

申请号：US793402

申请日：1985-10-31

申请人： Bao-Tai Hwang ,  Wendy A. Orr-Arienzo ,  Reinhard Glang

发明人： Bao-Tai Hwang ,  Wendy A. Orr-Arienzo ,  Reinhard Glang

IPC分类号： H01L21/306 ,  H01L21/308 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/30604 ,  H01L21/3081 ,  H01L21/3085

摘要： The present invention provides an improved etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions. The composition of the etchant is 0.2-6 mole % hydrofluoric acid, 14-28 mole % nitric acid, and 66-86 mole % acetic acid/water. The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.

摘要翻译： 本发明提供了一种改进的蚀刻剂组成和方法，用于覆盖本征或轻掺杂晶体区域的掺杂硅膜的电阻率特异性蚀刻。 蚀刻剂的组成为0.2-6摩尔％氢氟酸，14-28摩尔％硝酸和66-86摩尔％乙酸/水。 蚀刻剂不留下硅残留物，并且在轻掺杂或固有区域提供用蚀刻停止层的受控蚀刻。

公开(公告)号：US4048350A

公开(公告)日：1977-09-13

申请号：US615040

申请日：1975-09-19

申请人： Reinhard Glang ,  Stanley Irwin Raider

发明人： Reinhard Glang ,  Stanley Irwin Raider

IPC分类号： H01L29/73 ,  H01L21/22 ,  H01L21/283 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78 ,  H01L21/461

CPC分类号： H01L21/3115 ,  H01L29/0638 ,  Y10S438/91

摘要： Surface leakage paths on bipolar and FET transistors may be significantly reduced by the presence of a fixed charge in an insulating layer adhered to a semiconductor wafer. The fixed charge consists of ions which are introduced into the insulating layer after all high-temperature process treatments have been performed on the wafer. The ions are introduced into the insulating layer by (1) immersing the wafer in a solution of a suitable metal salt; (2) sandwiching the wafers between carefully cleaned non-immersed wafers and (3) driving the ions to the insulating layer-wafer interface by heating the wafer stacks in a furnace at a preselected temperature. The effective charge level embedded in the insulating layer is sufficient to protect against inversion of the wafer surface due to conductors on the insulating layer having negative potentials exceeding 10 volts and overlying the stored-charge area.

摘要翻译： 双极和FET晶体管的表面泄漏路径可能通过在粘附到半导体晶片的绝缘层中存在固定电荷而显着降低。 固定电荷由在晶片上进行所有高温处理处理之后被引入绝缘层中的离子组成。 通过（1）将晶片浸入合适的金属盐溶液中，将离子引入绝缘层; （2）将晶片夹在仔细清洁的非浸没晶片之间，以及（3）通过在预选温度下在炉中加热晶片叠层将离子驱动到绝缘层 - 晶片界面。 嵌入在绝缘层中的有效电荷水平足以防止由于绝缘层上的导体超过10伏并且覆盖存储电荷区域的晶片表面反转。

公开(公告)号：US4871684A

公开(公告)日：1989-10-03

申请号：US114190

申请日：1987-10-29

申请人： Reinhard Glang ,  San-Mei Ku

发明人： Reinhard Glang ,  San-Mei Ku

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/28525 ,  H01L21/8222 ,  H01L29/0804

摘要： A semiconductor process for fabricating bipolar devices of one type and extendible to include bipolar devices of a second type in the same epi-layer. The process protects selected surfaces of the epi-layer against deleterious processes associated with the formation of future emitter/contact regions for the devices. Subsequently, such emitter/contact regions are formed beneath such protected surfaces and contribute to enhanced device performance. The process also provides improved planarization of an insulating layer on the epi-layer by chemical-mechanical polishing. The planarization in conjunction with a mask formed in the insulating layer facilitates the formation of self-aligned emitter/base regions to appropriate thicknesses for high performance devices.

公开(公告)号：US4467519A

公开(公告)日：1984-08-28

申请号：US384371

申请日：1982-04-01

申请人： Reinhard Glang ,  San-Mei Ku ,  Alfred Schmitt

发明人： Reinhard Glang ,  San-Mei Ku ,  Alfred Schmitt

IPC分类号： H01L29/73 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/01 ,  H01L27/04 ,  H01L21/263 ,  H01L21/26 ,  H01L21/425

CPC分类号： H01L28/20 ,  H01L21/32155 ,  H01L21/8222

摘要： A method for fabricating polycrystalline silicon resistors is described which includes deposition of a polycrystalline silicon layer of very fine grain size upon an insulator surface, followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between about 800.degree. C. to 1100.degree. C. for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts are now made to the polycrystalline silicon layer to form the resistor.

摘要翻译： 描述了一种用于制造多晶硅电阻器的方法，其包括在绝缘体表面上沉积非常细晶粒尺寸的多晶硅层，然后将硼等离子注入等于或稍微超过多晶硅的溶解度极限。 这种离子注入通常使用屏幕二氧化硅表面层进行。 该结构可以在约800℃至1100℃的温度下退火15至180分钟以控制多晶硅层的晶粒尺寸，使硼离子在整个膜厚度上的分布均匀化并提高 硅颗粒中硼的浓度达到固溶度极限。 现在，将合适的电接触件制成多晶硅层以形成电阻器。