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公开(公告)号：US07818496B2
公开(公告)日：2010-10-19
申请号：US11731755
申请日：2007-03-30
申请人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
发明人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
CPC分类号： G06F12/0802 , G06F12/0875 , G06F2212/601
摘要： In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.
摘要翻译： 在一些实施例中，一种装置包括支持系统管理模式，系统管理存储器和存储器的软件可控高速缓存，一个或多个存储器模块，存储器控制器和通信总线的一个或多个处理器，以耦合一个或多个存储器模块 到内存控制器。 可以描述其他实施例。
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公开(公告)号：US20080244191A1
公开(公告)日：2008-10-02
申请号：US11731755
申请日：2007-03-30
申请人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
发明人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0875 , G06F2212/601
摘要： In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.
摘要翻译： 在一些实施例中，一种装置包括支持系统管理模式，系统管理存储器和存储器的软件可控高速缓存，一个或多个存储器模块，存储器控制器和通信总线的一个或多个处理器，以耦合一个或多个存储器模块 到内存控制器。 可以描述其他实施例。
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公开(公告)号：US20140189408A1
公开(公告)日：2014-07-03
申请号：US13730573
申请日：2012-12-28
申请人： Robert Gough , Mazen Gedeon , Barnes Cooper , Basavaraj Astekar
发明人： Robert Gough , Mazen Gedeon , Barnes Cooper , Basavaraj Astekar
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3215 , G06F1/3259 , G06F1/3265 , G06F1/3271 , Y02D10/153 , Y02D10/155 , Y02D10/156 , Y02D10/171
摘要： Particular embodiments described herein can offer an apparatus that includes logic, the logic at least partially comprising hardware logic to receive a first notification indicating that at least one first user interaction device has become precluded; and cause, by a processor and absent intermediate operation of operating system software, disabling of at least one second user interaction device based, at least in part, on the first notification.
摘要翻译： 本文描述的特定实施例可以提供包括逻辑的装置，所述逻辑至少部分地包括用于接收指示至少一个第一用户交互装置已被排除的第一通知的硬件逻辑; 并且由处理器引起并且不存在操作系统软件的中间操作，至少部分地基于第一通知来禁用至少一个第二用户交互设备。
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公开(公告)号：US20090006658A1
公开(公告)日：2009-01-01
申请号：US11823845
申请日：2007-06-28
申请人： Robert Gough , Barnes Cooper
发明人： Robert Gough , Barnes Cooper
IPC分类号： G06F3/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described.
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公开(公告)号：US20110302626A1
公开(公告)日：2011-12-08
申请号：US13213353
申请日：2011-08-19
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
IPC分类号： H04L29/06
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
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公开(公告)号：US20110078473A1
公开(公告)日：2011-03-31
申请号：US12960277
申请日：2010-12-03
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译： 在一些实施例中，电子设备包括至少一个处理器，多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎，从等待时间数据计算最小等待时间容差值，以及 从最小延迟容限值确定电源管理策略。
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公开(公告)号：US07546409B2
公开(公告)日：2009-06-09
申请号：US11823845
申请日：2007-06-28
申请人： Robert Gough , Barnes Cooper
发明人： Robert Gough , Barnes Cooper
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described.
摘要翻译： 在一些实施例中，系统包括USB主机系统，其包括USB功能驱动器和经由USB接口耦合到USB主机系统的USB设备，其中所述USB设备通过传递控制消息来协作来推迟一个或多个数据业务交换 边带通信链路。 可以描述其他实施例。
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8.发明申请SYSTEM AND METHOD FOR CAUSING REDUCED POWER CONSUMPTION ASSOCIATED WITH THERMAL REMEDIATION 有权引起与热修复相关的减少功耗的系统和方法公开(公告)号：US20140189390A1
公开(公告)日：2014-07-03
申请号：US13730386
申请日：2012-12-28
申请人： Robert Gough , Barnes Cooper , Basavaraj Astekar , Mazen Gedeon , Soethiha Soe
发明人： Robert Gough , Barnes Cooper , Basavaraj Astekar , Mazen Gedeon , Soethiha Soe
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.
摘要翻译： 本文描述的特定实施例可以提供一种方法，其包括接收指示至少一个设备是否处于低功率模式的信号，至少部分地基于所述信号确定所述至少一个设备处于第一热良性状态 ，以及执行与降低的热修复功率消耗相关联的第一操作。
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公开(公告)号：US20140181563A1
公开(公告)日：2014-06-26
申请号：US13726485
申请日：2012-12-24
申请人： Neil Songer , Barnes Cooper , Robert Gough , Jaya Jeyaseelan , William Knolla
发明人： Neil Songer , Barnes Cooper , Robert Gough , Jaya Jeyaseelan , William Knolla
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3265 , Y02D10/152 , Y02D10/153
摘要： Particular embodiments described herein can offer a method that includes determining that a first reported latency tolerance associated with at least one first device has not been received, and causing determination of a platform latency tolerance based, at least in part, on a first predefined latency tolerance, which is to serve as a substitute for the first reported latency tolerance.
摘要翻译： 本文描述的特定实施例可以提供一种方法，其包括确定尚未接收到与至少一个第一设备相关联的第一报告延迟容限，并且至少部分地基于第一预定义延迟容限来确定平台等待时间容限 ，这是替代第一次报告的延迟容忍度。
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10.发明授权Operating system-independent method and system of determining CPU utilization 有权操作系统独立的方法和确定CPU利用率的系统公开(公告)号：US07694164B2
公开(公告)日：2010-04-06
申请号：US10251202
申请日：2002-09-20
IPC分类号： G06F1/04
CPC分类号： G06F1/3203
摘要： A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.
摘要翻译： 提供了一种方法和装置来监视来自CPU核心的时钟控制信号; 并根据时钟控制信号计算CPU核心被采用执行工作的采样间隔期间的时间段。
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