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1.发明申请SYSTEM AND METHOD FOR CAUSING REDUCED POWER CONSUMPTION ASSOCIATED WITH THERMAL REMEDIATION 有权引起与热修复相关的减少功耗的系统和方法公开(公告)号：US20140189390A1
公开(公告)日：2014-07-03
申请号：US13730386
申请日：2012-12-28
申请人： Robert Gough , Barnes Cooper , Basavaraj Astekar , Mazen Gedeon , Soethiha Soe
发明人： Robert Gough , Barnes Cooper , Basavaraj Astekar , Mazen Gedeon , Soethiha Soe
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.
摘要翻译： 本文描述的特定实施例可以提供一种方法，其包括接收指示至少一个设备是否处于低功率模式的信号，至少部分地基于所述信号确定所述至少一个设备处于第一热良性状态 ，以及执行与降低的热修复功率消耗相关联的第一操作。
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公开(公告)号：US20140189408A1
公开(公告)日：2014-07-03
申请号：US13730573
申请日：2012-12-28
申请人： Robert Gough , Mazen Gedeon , Barnes Cooper , Basavaraj Astekar
发明人： Robert Gough , Mazen Gedeon , Barnes Cooper , Basavaraj Astekar
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3215 , G06F1/3259 , G06F1/3265 , G06F1/3271 , Y02D10/153 , Y02D10/155 , Y02D10/156 , Y02D10/171
摘要： Particular embodiments described herein can offer an apparatus that includes logic, the logic at least partially comprising hardware logic to receive a first notification indicating that at least one first user interaction device has become precluded; and cause, by a processor and absent intermediate operation of operating system software, disabling of at least one second user interaction device based, at least in part, on the first notification.
摘要翻译： 本文描述的特定实施例可以提供包括逻辑的装置，所述逻辑至少部分地包括用于接收指示至少一个第一用户交互装置已被排除的第一通知的硬件逻辑; 并且由处理器引起并且不存在操作系统软件的中间操作，至少部分地基于第一通知来禁用至少一个第二用户交互设备。
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公开(公告)号：US20190033953A1
公开(公告)日：2019-01-31
申请号：US15819552
申请日：2017-11-21
申请人： Vijaykumar B. Kadgi , Barnes Cooper , Nivedita Aggarwal , Venkataramani Gopalakrishnan , Jenn Chuan Cheng , Basavaraj Astekar , Charuhasini Sunderraman , Han Kung Chua , Anil Baby , Tin-Cheung Kung , Chia-Hung Kuo
发明人： Vijaykumar B. Kadgi , Barnes Cooper , Nivedita Aggarwal , Venkataramani Gopalakrishnan , Jenn Chuan Cheng , Basavaraj Astekar , Charuhasini Sunderraman , Han Kung Chua , Anil Baby , Tin-Cheung Kung , Chia-Hung Kuo
摘要： Techniques are provided for managing power delivery to multiple universal serial bus (USB) type-C ports of a desktop computer system. In an example, a method can include providing a first power level to a USB power delivery controller during a non-sleep mode operation of the desktop computer, and providing a second power level to the USB power delivery controller when the computer is in a sleep mode, the second power level configured to provide default charge power to a connected device when the computer is in the sleep mode.
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公开(公告)号：US08332675B2
公开(公告)日：2012-12-11
申请号：US13213353
申请日：2011-08-19
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译： 在一些实施例中，电子设备包括至少一个处理器，多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎，从等待时间数据计算最小等待时间容差值，以及 从最小延迟容限值确定电源管理策略。
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公开(公告)号：US07606962B2
公开(公告)日：2009-10-20
申请号：US11975841
申请日：2007-10-22
申请人： Robert Gough , Barnes Cooper
发明人： Robert Gough , Barnes Cooper
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described.
摘要翻译： 在一些实施例中，系统包括主机系统，其包括工业标准接口，经由工业标准接口耦合到主机设备的外围设备以及主机系统中的逻辑，以确认主机设备支持增强特征，至少识别 可以在其上实现增强特征的工业标准接口上的一个引脚，使得能够支持至少一个引脚上的增强特征，并将与增强特征相关联的通信流量路由到至少一个引脚。 可以描述其他实施例。
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公开(公告)号：US20090006704A1
公开(公告)日：2009-01-01
申请号：US11975841
申请日：2007-10-22
申请人： Robert Gough , Barnes Cooper
发明人： Robert Gough , Barnes Cooper
IPC分类号： G06F13/14
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described.
摘要翻译： 在一些实施例中，系统包括主机系统，其包括工业标准接口，经由工业标准接口耦合到主机设备的外围设备以及主机系统中的逻辑，以确认主机设备支持增强特征，至少识别 可以在其上实现增强特征的工业标准接口上的一个引脚，使得能够支持至少一个引脚上的增强特征，并将与增强特征相关联的通信流量路由到至少一个引脚。 可以描述其他实施例。
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公开(公告)号：US20080244191A1
公开(公告)日：2008-10-02
申请号：US11731755
申请日：2007-03-30
申请人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
发明人： Barnes Cooper , Isaac Oram , Kirk Brannock , Robert Gough
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0875 , G06F2212/601
摘要： In some embodiments, an apparatus comprises one or more processors supporting a system management mode, system management memory, and software controllable caching of memory, one or more memory modules, a memory controller, and a communication bus to couple the one or more memory modules to the memory controller. Other embodiments may be described.
摘要翻译： 在一些实施例中，一种装置包括支持系统管理模式，系统管理存储器和存储器的软件可控高速缓存，一个或多个存储器模块，存储器控制器和通信总线的一个或多个处理器，以耦合一个或多个存储器模块 到内存控制器。 可以描述其他实施例。
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公开(公告)号：US20090006658A1
公开(公告)日：2009-01-01
申请号：US11823845
申请日：2007-06-28
申请人： Robert Gough , Barnes Cooper
发明人： Robert Gough , Barnes Cooper
IPC分类号： G06F3/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： In some embodiments, a system comprises a USB host system comprising a USB function driver, and a USB device coupled to the USB host system via a USB interface, wherein the USB device cooperate to defer one or more data traffic exchanges by passing control messages via a sideband communication link. Other embodiments may be described.
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公开(公告)号：US20110302626A1
公开(公告)日：2011-12-08
申请号：US13213353
申请日：2011-08-19
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
IPC分类号： H04L29/06
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
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公开(公告)号：US20110078473A1
公开(公告)日：2011-03-31
申请号：US12960277
申请日：2010-12-03
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jevaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译： 在一些实施例中，电子设备包括至少一个处理器，多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎，从等待时间数据计算最小等待时间容差值，以及 从最小延迟容限值确定电源管理策略。
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