专利检索 ap:("Been-Yih Jin" OR "Brian S. Doyle" OR "Scott A. Hareland" OR "Mark L. Doczy" OR "Matthew V. Metz" OR "Boyan I. Boyanov" OR "Suman Datta" OR "Jack T. Kavalieros" OR "Robert S. Chau") AND inv:"Been-Yih Jin" 第 1 页

1.

发明授权
Semiconductor channel on insulator structure 有权
标题翻译：半导体通道绝缘体结构

公开(公告)号：US07235809B2

公开(公告)日：2007-06-26

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau

发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

2.

发明授权
Semiconductor channel on insulator structure 有权
标题翻译：半导体通道绝缘体结构

公开(公告)号：US07138316B2

公开(公告)日：2006-11-21

申请号：US10669064

申请日：2003-09-23

申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau

发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

3.

发明申请
EXTREME HIGH MOBILITY CMOS LOGIC 有权
标题翻译：极高的移动性CMOS逻辑

公开(公告)号：US20140291615A1

公开(公告)日：2014-10-02

申请号：US14302371

申请日：2014-06-11

申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L27/092 , H01L29/15

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

4.

发明申请
EXTREME HIGH MOBILITY CMOS LOGIC 有权
标题翻译：极高的移动性CMOS逻辑

公开(公告)号：US20120199813A1

公开(公告)日：2012-08-09

申请号：US13450359

申请日：2012-04-18

申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L27/092 , H01L21/8238

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

5.

发明授权
Extreme high mobility CMOS logic 有权
标题翻译：极高移动性CMOS逻辑

公开(公告)号：US08518768B2

公开(公告)日：2013-08-27

申请号：US13450359

申请日：2012-04-18

申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L21/70 , H01L21/8238

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

6.

发明授权
Extreme high mobility CMOS logic 有权
标题翻译：极高移动性CMOS逻辑

公开(公告)号：US08802517B2

公开(公告)日：2014-08-12

申请号：US13962890

申请日：2013-08-08

申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L21/338

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

7.

发明申请
EXTREME HIGH MOBILITY CMOS LOGIC 有权
标题翻译：极高的移动性CMOS逻辑

公开(公告)号：US20130328015A1

公开(公告)日：2013-12-12

申请号：US13962890

申请日：2013-08-08

申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L27/092 , H01L21/8238

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

8.

发明授权
Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权
标题翻译：隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域

公开(公告)号：US07888221B2

公开(公告)日：2011-02-15

申请号：US12229459

申请日：2008-08-22

申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau

发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/7391

摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。

9.

发明授权
Extreme high mobility CMOS logic 有权
标题翻译：极高移动性CMOS逻辑

公开(公告)号：US08183556B2

公开(公告)日：2012-05-22

申请号：US11305452

申请日：2005-12-15

申请人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

发明人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau

IPC分类号： H01L21/84

CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783

摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

10.

发明申请
Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权
标题翻译：隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域

公开(公告)号：US20080318385A1

公开(公告)日：2008-12-25

申请号：US12229459

申请日：2008-08-22

申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau

发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/7391

摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区域。

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