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公开(公告)号：US20060292776A1
公开(公告)日：2006-12-28
申请号：US11167647
申请日：2005-06-27
申请人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
发明人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
IPC分类号： H01L21/8234 , H01L21/20 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L27/0922 , H01L29/1054 , H01L29/165 , H01L29/7848
摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.
摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。 所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。 施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。
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公开(公告)号：US20080237636A1
公开(公告)日：2008-10-02
申请号：US11729564
申请日：2007-03-29
IPC分类号： H01L29/778
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/7787 , H01L29/7843 , H01L29/7851
摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.
摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。
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公开(公告)号：US07569869B2
公开(公告)日：2009-08-04
申请号：US11729564
申请日：2007-03-29
IPC分类号： H01L29/737 , H01L29/778
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/7787 , H01L29/7843 , H01L29/7851
摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.
摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。
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公开(公告)号：US20100200835A1
公开(公告)日：2010-08-12
申请号：US12762585
申请日：2010-04-19
IPC分类号： H01L29/16 , H01L21/762 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。
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公开(公告)号：US07727830B2
公开(公告)日：2010-06-01
申请号：US12006273
申请日：2007-12-31
IPC分类号： H01L21/337
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。
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公开(公告)号：US08110458B2
公开(公告)日：2012-02-07
申请号：US12762585
申请日：2010-04-19
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。
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公开(公告)号：US20090170251A1
公开(公告)日：2009-07-02
申请号：US12006273
申请日：2007-12-31
IPC分类号： H01L21/8234
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66477 , H01L29/78684 , H01L29/78696
摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。
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