公开(公告)号：US20060292776A1

公开(公告)日：2006-12-28

申请号：US11167647

申请日：2005-06-27

申请人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

发明人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

IPC分类号： H01L21/8234 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7848

摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.

摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。 所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。 施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。

公开(公告)号：US20070069302A1

公开(公告)日：2007-03-29

申请号：US11238445

申请日：2005-09-28

申请人： Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

发明人： Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7851 ,  H01L29/78684

摘要： A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

摘要翻译： 利用对pMOS和nMOS晶体管具有单功函数的公共栅电极材料的方法，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。

公开(公告)号：US20060081932A1

公开(公告)日：2006-04-20

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

公开(公告)号：US20050064616A1

公开(公告)日：2005-03-24

申请号：US10669064

申请日：2003-09-23

申请人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L29/786 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US20060051882A1

公开(公告)日：2006-03-09

申请号：US11210220

申请日：2005-08-22

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060166447A1

公开(公告)日：2006-07-27

申请号：US11390892

申请日：2006-03-27

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/336

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060060930A1

公开(公告)日：2006-03-23

申请号：US10943693

申请日：2004-09-17

申请人： Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/7833

摘要： Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.

摘要翻译： 可以通过原子层沉积形成由铪或二氧化锆的硅酸盐形成的栅极电介质。 原子层沉积的前体可以包括氧化剂，硅酸盐前体和锆或铪前体。

公开(公告)号：US20060045968A1

公开(公告)日：2006-03-02

申请号：US10925573

申请日：2004-08-25

申请人： Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： C23C16/00

CPC分类号： C23C16/45527

摘要： Increasing the number of successive pulses of oxidant before applying pulses of metal precursor may improve the quality of the resulting metal or rare earth oxide films. These metal or rare earth oxide films may be utilized for high dielectric constant gate dielectrics. In addition, pulsing the oxidant during the pre-stabilization period may be advantageous. Also, using more pulses of oxidant than the pulses of precursor may reduce chlorine concentration in the resulting films.

摘要翻译： 在施加金属前体的脉冲之前增加氧化剂的连续脉冲数可以提高所得金属或稀土氧化物膜的质量。 这些金属或稀土氧化物膜可用于高介电常数栅极电介质。 此外，在预稳定化期间脉冲氧化剂可能是有利的。 此外，使用比前体脉冲更多的氧化剂脉冲可以降低所得膜中的氯浓度。

公开(公告)号：US20060051880A1

公开(公告)日：2006-03-09

申请号：US10935784

申请日：2004-09-07

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060286755A1

公开(公告)日：2006-12-21

申请号：US11154138

申请日：2005-06-15

申请人： Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

发明人： Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

IPC分类号： H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。