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公开(公告)号：US20080237636A1
公开(公告)日：2008-10-02
申请号：US11729564
申请日：2007-03-29
IPC分类号： H01L29/778
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/7787 , H01L29/7843 , H01L29/7851
摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.
摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。
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公开(公告)号：US07569869B2
公开(公告)日：2009-08-04
申请号：US11729564
申请日：2007-03-29
IPC分类号： H01L29/737 , H01L29/778
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/7787 , H01L29/7843 , H01L29/7851
摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.
摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。
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3.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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4.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US07902014B2
公开(公告)日：2011-03-08
申请号：US11649545
申请日：2007-01-03
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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5.发明申请Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号：US20080318385A1
公开(公告)日：2008-12-25
申请号：US12229459
申请日：2008-08-22
申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7391
摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区域。
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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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7.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US08264004B2
公开(公告)日：2012-09-11
申请号：US12715034
申请日：2010-03-01
IPC分类号： H01L29/778
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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公开(公告)号：US20120199813A1
公开(公告)日：2012-08-09
申请号：US13450359
申请日：2012-04-18
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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9.发明授权Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号：US07888221B2
公开(公告)日：2011-02-15
申请号：US12229459
申请日：2008-08-22
申请人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人： Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/7391
摘要： The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译： 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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10.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US07713803B2
公开(公告)日：2010-05-11
申请号：US11731266
申请日：2007-03-29
IPC分类号： H01L21/336
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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