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公开(公告)号：US20220302911A1
公开(公告)日：2022-09-22
申请号：US17836419
申请日：2022-06-09
发明人： Xiangye WEI , Liming XIU , Yuhai MA
IPC分类号： H03K5/1252 , G06F1/04 , H03K5/00
摘要： A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit (10) includes a control circuit (11) and a signal generation circuit (12). The control circuit (11) is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit (12) is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.
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公开(公告)号：US20210226618A1
公开(公告)日：2021-07-22
申请号：US16633298
申请日：2019-01-02
发明人： Xiangye WEI , Liming XIU
摘要： A measuring device and a measuring method are provided. The measuring device includes an oscillating circuit, a time average frequency-frequency lock loop, and a digital signal processing circuit. The oscillation circuit includes an element to be measured and is configured to output a signal having an oscillation frequency correlated with an element value of the element to be measured. The time average frequency-frequency lock loop is configured to receive the signal output by the oscillation circuit and output a frequency control word correlated with the oscillation frequency. The digital signal processing circuit is configured to read the frequency control word output by the time average frequency-frequency lock loop and obtain the element value of the element to be measured according to the read frequency control word. The measuring device is easy to integrate, has small volume, low power consumption, and high reliability, and can achieve high-precision measurement.
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3.发明公开公开(公告)号：US20240048540A1
公开(公告)日：2024-02-08
申请号：US18266690
申请日：2020-12-24
发明人： Xiangye WEI , Yiming BAI , Liming XIU
CPC分类号： H04L63/0457 , H04L9/3278
摘要： Provided is an interactive authentication method, applicable to a transmitter. The transmitter is communicatively connected to a receiver. The authentication method includes: generating a first challenge and transmitting the first challenge to the receiver; receiving a response from the receiver, wherein the response comprises first identity authentication information and a second challenge, the first identity authentication information and the second challenge being encrypted using a first identity authentication key; generating, based on the first challenge, a second identity authentication key and second identity authentication information; and decrypting the first identity authentication information using the second identity authentication key, and performing identity authentication by matching the decrypted first identity authentication information with the second identity authentication information.
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公开(公告)号：US20220318185A1
公开(公告)日：2022-10-06
申请号：US17427235
申请日：2020-10-27
发明人： Xiangye WEI , Liming XIU
摘要： A data processing circuit, a data processing method, and an electronic device are provided. The data processing circuit includes a first data processing sub-circuit and a second data processing sub-circuit. An output terminal of the first data processing sub-circuit is connected to an input terminal of the second data processing sub-circuit. The first data processing sub-circuit is configured to receive an original sequence to generate a first processed sequence. Each of first processed numbers in the first processed sequence is calculated from at least two pieces of original data in the original data. The second data processing sub-circuit is configured to receive the first processed sequence to generate a second processed sequence.
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公开(公告)号：US20220311606A1
公开(公告)日：2022-09-29
申请号：US17297540
申请日：2020-06-10
发明人： Yiming BAI , Xiangye WEI , Liming XIU , Xin LI
IPC分类号： H04L9/08 , H04B10/116 , H04B10/508 , H04L9/14
摘要： The optical communication apparatus includes a random number generator, a first key manager, a first encryption and decryption device, a driver and a transmitter. The random number generator is configured to generate a random number based on a time frequency. The first key manager is configured to generate a first key based on the random number, store and manage the first key and a second key obtained from an outside. The first encryption and decryption device is configured to encrypt the first key according to the second key to obtain a first encrypted key, and is configured to encrypt initial communication data according to the first key to obtain encrypted data. The driver is configured to obtain the encrypted data and encode the encrypted data into a visible light emission instruction. The first transmitter is configured to receive the visible light emission instruction and emit first visible light.
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公开(公告)号：US20220311529A1
公开(公告)日：2022-09-29
申请号：US17413367
申请日：2020-01-19
发明人： Xiangye WEI , Liming XIU , Yiming BAI
摘要： There is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.
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公开(公告)号：US20220173739A1
公开(公告)日：2022-06-02
申请号：US17515233
申请日：2021-10-29
发明人： Xiangye WEI , Liming XIU
摘要： An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.
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8.发明公开公开(公告)号：US20240089003A1
公开(公告)日：2024-03-14
申请号：US17767763
申请日：2021-03-09
发明人： Xiangye WEI , Liming XIU , Yiming BAI , Xin LI
IPC分类号： H04B10/50
CPC分类号： H04B10/502
摘要： An optical communication device, an optical communication system, and a method for establishing a communication connection are provided, relating to communications technology. In the optical communication device, the first driving circuit can control, based on the generated first target plaintext, the optical signal transmitting circuit to transmit the first optical signal, and control, based on the generated first key, the optical signal transmitting circuit to transmit the second optical signal. That is, an optical communication device that detects the optical signals can establish, based on the optical signals, a communication connection with the optical communication device that transmits the optical signals.
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公开(公告)号：US20240078201A1
公开(公告)日：2024-03-07
申请号：US18271865
申请日：2022-07-01
发明人： Xiangye WEI , Liming XIU
CPC分类号： G06F13/1689 , G06F5/10 , G06F13/1621
摘要： Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.
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公开(公告)号：US20230403166A1
公开(公告)日：2023-12-14
申请号：US18033807
申请日：2020-10-28
发明人： Xiangye WEI , Liming XIU
IPC分类号： H04L9/32
CPC分类号： H04L9/3278 , H04L9/3236
摘要： A data processing method, including: obtaining a challenge sequence of challenge-response pairs, and generating, by a physical unclonable function, an original response sequence corresponding to the challenge-response pairs; generating a first index parameter according to the challenge sequence, and obtaining feature bit information in the original response sequence according to the first index parameter; converting the challenge sequence to generate a second index parameter, and updating the first index parameter according to the second index parameter and the feature bit information; obtaining new feature bit information in the original response sequence according to the updated first index parameter; and repeatedly generating second index parameters, updating the first index parameter according to the second index parameters and the latest obtained feature bit information, and obtaining multiple pieces of feature bit information, to generate a target response sequence according to the multiple pieces of feature bit information.
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