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136 条记录 (耗时 0.036 秒)

    Stacked semiconductor module
    6.
    发明授权
    Stacked semiconductor module 有权
    堆叠式半导体模块

    公开(公告)号：US07285443B2

    公开(公告)日：2007-10-23

    申请号：US11378008

    申请日：2006-03-16

    申请人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    发明人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C29/08 ,  G11C2029/4402 ,  H01L23/5382 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

    摘要翻译： 提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。 半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。 可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。 此外，提供了一种用于访问半导体模块的方法。 提供上述壳体以包围多个集成电路芯片和可编程存储器件。 然后识别满足预定标准的多个集成电路芯片的集成电路芯片。 随后编程可编程存储器件以识别所选择的集成电路芯片。

    Clock routing in multiple channel modules and bus systems
    8.
    发明授权
    Clock routing in multiple channel modules and bus systems 失效

    公开(公告)号：US07027307B2

    公开(公告)日：2006-04-11

    申请号：US10420308

    申请日：2003-04-22

    申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

    Clock routing in multiple channel modules and bus systems
    9.
    发明申请
    Clock routing in multiple channel modules and bus systems 失效
    多通道模块和总线系统中的时钟路由

    公开(公告)号：US20050254221A1

    公开(公告)日：2005-11-17

    申请号：US11190561

    申请日：2005-07-26

    申请人： Ravindranath Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： G06F13/40 ,  G11C5/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K7/06 ,  H05K7/14

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard

    摘要翻译： 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板

    Clock Routing in Mulitiple Channel Modules and Bus Systems
    10.
    发明申请
    Clock Routing in Mulitiple Channel Modules and Bus Systems 审中-公开
    多通道模块和总线系统中的时钟路由

    公开(公告)号：US20120001670A1

    公开(公告)日：2012-01-05

    申请号：US13235251

    申请日：2011-09-16

    申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： G06F1/04

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

    摘要翻译： 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板。