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公开(公告)号:US07170314B2
公开(公告)日:2007-01-30
申请号:US11054955
申请日:2005-02-11
申请人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Crag E. Hampel , Wai-Yeng Yip
发明人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Crag E. Hampel , Wai-Yeng Yip
IPC分类号: H03K17/16 , H03K19/003
CPC分类号: G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译: 公开了可用于实现具有1至N个信道的模块的各种模块结构。 总线系统可以通过这种模块的互连形成。
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公开(公告)号:US06898085B2
公开(公告)日:2005-05-24
申请号:US10695854
申请日:2003-10-30
申请人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
发明人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
IPC分类号: G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14 , H05K7/02 , H05K7/10
CPC分类号: G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
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公开(公告)号:US06765800B2
公开(公告)日:2004-07-20
申请号:US09839642
申请日:2001-04-20
申请人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
发明人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
IPC分类号: H05K702
CPC分类号: G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译: 公开了可用于实现具有1至N个信道的模块的各种模块结构。 总线系统可以通过这种模块的互连形成。
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公开(公告)号:US08634452B2
公开(公告)日:2014-01-21
申请号:US13491508
申请日:2012-06-07
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号: H04B17/00
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译: 集成电路装置包括:第一电路,用于接收与电输入信号的第一数据周期相关联的位,可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路,用于接收与第 电输入信号的第二周期,以产生关于与第二数据周期相关联的位的逻辑状态的判定。 均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰,并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰,该电路可操作以产生关于位的逻辑状态的判定 的电气输入信号。
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公开(公告)号:US5430676A
公开(公告)日:1995-07-04
申请号:US202290
申请日:1994-02-25
申请人: Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人: Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号: G06F13/16 , G11C5/06 , G11C11/401 , G06F12/00
CPC分类号: G11C5/066
摘要: As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
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公开(公告)号:US07124221B1
公开(公告)日:2006-10-17
申请号:US09478916
申请日:2000-01-06
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译: 存储系统使用多脉冲幅度调制(多PAM)输出驱动器和接收器来发送和接收多PAM信号。 多PAM信号具有两个以上的电压电平,每个数据间隔现在以有效电压电平之一发送“符号”。 在一个实施例中,符号表示两个或更多位。 多PAM输出驱动器将输出符号驱动到信号线上。 输出符号表示包括最高有效位(MSB)和最低有效位(LSB)的至少两个位。 多PAM接收器从信号线接收输出符号,并确定MSB和LSB。
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公开(公告)号:US5434817A
公开(公告)日:1995-07-18
申请号:US333869
申请日:1994-11-03
申请人: Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人: Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号: G06F13/16 , G11C5/06 , G11C11/401 , G11C7/00 , G06F12/06
CPC分类号: G11C5/066
摘要: As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
摘要翻译: 随着与DRAM的接口变得越来越先进和更高的性能,支持接口所需的接口和信号线变得越来越昂贵。 因此,为了利用接口中的信号线的高性能,期望使信号线的数量最小化并且使与DRAM接口的信号线的带宽最大化。 在本发明的DRAM存储器系统中,地址和控制线被组合并且被多路复用的信息使得DRAM引脚始终具有大致相等的信息速率。
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公开(公告)号:US07809088B2
公开(公告)日:2010-10-05
申请号:US12624365
申请日:2009-11-23
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.
摘要翻译: 用于补偿输入信号采样中的符号间干扰的多相接收机包括:第一积分接收器,用于在时钟的第一相位上对输入信号的数据进行积分和采样;以及第二积分接收器,对输入信号的数据进行积分和采样 在时钟的第二阶段。 多相接收机还包括均衡电路,用于根据先前由不同于第一积分接收器的积分接收器接收的数据的积分结果来调整由第一积分接收器的积分,并根据结果调整由第二积分接收器的积分 对由先前由不同于第二积分接收器的积分接收器接收的数据的积分。
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公开(公告)号:US07626442B2
公开(公告)日:2009-12-01
申请号:US11368012
申请日:2006-03-03
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译: 存储系统使用多个脉冲幅度调制(多PAM)输出驱动器和接收器来发送和接收多PAM信号。 多PAM信号具有两个以上的电压电平,每个数据间隔现在以有效电压电平之一发送“符号”。 在一个实施例中,符号表示两个或更多位。 多PAM输出驱动器将输出符号驱动到信号线上。 输出符号表示包括最高有效位(MSB)和最低有效位(LSB)的至少两个位。 多PAM接收器从信号线接收输出符号并确定MSB和LSB。
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公开(公告)号:US06687780B1
公开(公告)日:2004-02-03
申请号:US09706238
申请日:2000-11-02
申请人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号: G06F1340
CPC分类号: G06F13/4072 , G06F13/4086 , G06F13/4243
摘要: A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.
摘要翻译: 与可寻址存储器一起使用的总线系统具有单向信号线的全局总线。 全球总线有一个第一端和一端。 主设备向全局总线发送数据并从全局总线接收数据。 第一和第二全局总线终端分别耦合到全局总线的第一和第二端。 一个或多个子系统通过全局总线彼此并联连接到主设备。 每个子系统包括本地总线,耦合到本地总线的一个或多个从设备,经由全局总线接收来自主设备的输入信号的写入缓冲器,并且经由本地总线将输入信号发送到一个或多个从设备, 以及读取缓冲器,其经由本地总线从一个或多个从设备接收输出信号,并经由全局总线将输出信号发送到主设备。
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