公开(公告)号：US06763486B2

公开(公告)日：2004-07-13

申请号：US09851731

申请日：2001-05-09

申请人： Benny W H Lai ,  Young Gon Kim ,  Kenneth P Parker ,  Jeff Rearick

发明人： Benny W H Lai ,  Young Gon Kim ,  Kenneth P Parker ,  Jeff Rearick

IPC分类号： G01R31317

CPC分类号： G01R31/318577 ,  G01R31/31855 ,  G01R31/318572

摘要： Boundary scan testing methods that detect manufacturing defects in AC-coupled differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one embodiment, the signal parameter is compared to reference parameter data provided by the transmitter. In a second embodiment, the reference parameter data is sent from an external source. All the components on board are synchronized with this external source. In a third embodiment, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.

摘要翻译： 检测AC耦合差分对中的制造缺陷的边界扫描测试方法可以基于所选择的信号参数：相位或频率。 数据由信号参数编码。 在一个实施例中，将信号参数与由发射机提供的参考参数数据进行比较。 在第二实施例中，从外部源发送参考参数数据。 板上的所有组件与此外部源同步。 在第三实施例中，参考参数数据被嵌入在发送器和接收器之间的每个AC信号中。 一条差分链路的两行用于发送不同的模式。

公开(公告)号：US07139955B2

公开(公告)日：2006-11-21

申请号：US10321758

申请日：2002-12-17

申请人： John G Rohrbaugh ,  Jeff Rearick

发明人： John G Rohrbaugh ,  Jeff Rearick

IPC分类号： G06F11/00 ,  G06F17/50 ,  G06F7/62

CPC分类号： G06F11/263 ,  G01R31/318371

摘要： Hierarchically-controlled automatic test pattern generation (ATPG) is provided. One embodiment comprises a method for automatically generating test patterns for testing a device under test. Briefly described, one such method comprises the steps of: receiving a hierarchical model of a device under test, the hierarchical model comprising at least one low-level design component and at least one high-level design component which contains the low-level design component; selecting a fault to be detected in the device under test; and performing an automatic test pattern generation (ATPG) algorithm on the design components based on the hierarchy of the hierarchical model.

摘要翻译： 提供了分层控制的自动测试模式生成（ATPG）。 一个实施例包括用于自动生成用于测试被测器件的测试图案的方法。 简要描述，一种这样的方法包括以下步骤：接收被测设备的层次模型，分层模型包括至少一个低级设计组件和至少一个包含低级设计组件的高级设计组件 ; 选择要在被测设备中检测到的故障; 并根据层次模型的层次对设计组件执行自动测试模式生成（ATPG）算法。

公开(公告)号：US06396312B1

公开(公告)日：2002-05-28

申请号：US09637534

申请日：2000-08-11

申请人： Shad R. Shepston ,  Jeff Rearick ,  John G Rohrbaugh

发明人： Shad R. Shepston ,  Jeff Rearick ,  John G Rohrbaugh

IPC分类号： H03B2100

CPC分类号： G04F10/04

摘要： A gate transition counter. A ring oscillator provides a plurality outputs, each delayed from the adjacent output by a gate delay. The outputs of the ring oscillator are captured by an array of latches upon receipt of a halt signal. The last latch drives a ripple counter. The preferred implementation uses five inverters in the ring oscillator so that each complete cycle of the ring oscillator represents ten gate delays. A ripple counter counts the number of gate delays by ten. The latch outputs and the ripple counter outputs can be converted to a binary representation of the number of gate delays to provide a count with the smallest time increment that can be produced by the circuit.

摘要翻译： 门过渡计数器。 环形振荡器提供多个输出，每个输出通过门延迟从相邻输出延迟。 在收到停止信号时，环形振荡器的输出由锁存器阵列捕获。 最后一个锁存器驱动纹波计数器。 优选的实施方案在环形振荡器中使用五个反相器，使得环形振荡器的每个完整周期表示十个门延迟。 纹波计数器将门延迟数量计数为十。 锁存器输出和纹波计数器输出可以转换为门延迟数的二进制表示，以提供可由电路产生的最小时间增量的计数。

公开(公告)号：US06707313B1

公开(公告)日：2004-03-16

申请号：US10369069

申请日：2003-02-19

申请人： John G Rohrbaugh ,  Jeff Rearick

发明人： John G Rohrbaugh ,  Jeff Rearick

IPC分类号： G01R3126

CPC分类号： G01R31/31813

摘要： Systems and methods for testing integrated circuits are provided. One such method comprises: providing a target fault list corresponding to an integrated circuit, the target fault list including at least a first fault and a second fault; measuring a relationship between the first fault and the second fault, the relationship corresponding to which of the first fault and the second fault is more readily detected by automatic test pattern generation; ordering the first fault and the second fault within the target fault list in a manner corresponding to the relationship; and performing automatic test pattern generation based upon an order of the faults of the target fault list. Systems and other methods also are provided.

摘要翻译： 提供了集成电路测试的系统和方法。 一种这样的方法包括：提供与集成电路相对应的目标故障列表，所述目标故障列表至少包括第一故障和第二故障; 测量第一故障和第二故障之间的关系，通过自动测试模式生成更容易地检测到与第一故障和第二故障中的哪一个相对应的关系; 以对应于该关系的方式对目标故障列表内的第一故障和第二故障进行排序; 并根据目标故障列表的故障顺序执行自动测试模式生成。 还提供了系统和其它方法。

公开(公告)号：US06380780B1

公开(公告)日：2002-04-30

申请号：US09585366

申请日：2000-06-01

申请人： Robert C. Aitken ,  Haluk Konuk ,  Jeff Rearick ,  John Stephen Walther

发明人： Robert C. Aitken ,  Haluk Konuk ,  Jeff Rearick ,  John Stephen Walther

IPC分类号： H03K3356

CPC分类号： H03K3/0375 ,  G01R31/318541

摘要： An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing. The FAST-lite flip-flop is so designated because it uses one less flip-flop than the prior art FAST flip-flop.

摘要翻译： 集成电路提供全自动扫描测试（FAST） - 触发器。 集成电路具有数据，扫描，主控，时钟，扫描到主机和主扫描输出输入。 第一晶体管电路连接到数据，主保持和时钟输入，并具有第一晶体管电路输出。 第二晶体管电路连接到罐入和扫描到主输入端，并具有第二晶体管电路输出。 第一触发器连接到第一晶体管电路，第二晶体管电路输出并具有第一触发器输出。 第三晶体管电路连接到第二晶体管电路输出和主到扫描输出，并具有第三晶体管电路输出。 第二触发器锁存器连接到第三晶体管电路输出具有第二触发器输出。 FAST-Lite触发器使用第一触发器和第二触发器的正常功能，以正常模式或测试模式进行扫描测试。 FAST-lite触发器如此被指定，因为它比现有技术的FAST触发器使用少一个触发器。

公开(公告)号：US06239607B1

公开(公告)日：2001-05-29

申请号：US09174501

申请日：1998-10-16

申请人： Peter Maxwell ,  Jeff Rearick

发明人： Peter Maxwell ,  Jeff Rearick

IPC分类号： G01R3126

CPC分类号： G01R31/2846

摘要： A method for operating a data processing system to provide an estimate of the leakage current expected from an integrated circuit having a known test vector applied thereto. The method generates a graph having a first node connected to a terminal maintained at a first power supply potential and a second node connected to a terminal maintained at a second power supply potential, the first and second power supply potentials having a potential difference of VDD. Each edge represents a source-drain connected transistor connected between two nodes as a switch having a resistance that depends on whether the transistor is “on” or “off” when the test signals are present. Each node in the graph is assigned a value of 0 or 1, together with the strength of that value. The assignment process also verifies that the circuit is in a valid static state. A leakage current estimate is generated for each path connecting the first and second nodes, and estimates are combined to arrive at the estimate for the integrated circuit. In one embodiment, the leakage current is calculated using an equation having eight components. Four of these represent the leakage current arising from N-type transistors in the circuit and the other four represent the leakage current arising from P-type transistors in the circuit.

摘要翻译： 一种用于操作数据处理系统以提供从具有施加到其上的已知测试矢量的集成电路预期的泄漏电流的估计的方法。 该方法生成具有连接到保持在第一电源电位的终端的第一节点和连接到维持在第二电源电位的终端的第二节点的图形，第一和第二电源电位具有VDD的电位差。 每个边缘表示连接在两个节点之间的源极 - 漏极连接的晶体管，作为具有取决于晶体管是否在测试信号存在时“导通”或“关闭”的电阻的开关。 图中的每个节点都被赋值为0或1，以及该值的强度。 分配过程还验证电路处于有效的静态状态。 对于连接第一和第二节点的每个路径产生泄漏电流估计，并且组合估计以得到集成电路的估计。 在一个实施例中，使用具有八个分量的方程来计算泄漏电流。 其中四个表示电路中N型晶体管产生的漏电流，另外四个表示电路中P型晶体管产生的漏电流。

公开(公告)号：US06895562B2

公开(公告)日：2005-05-17

申请号：US10228913

申请日：2002-08-27

申请人： John G Rohrbaugh ,  Jeff Rearick ,  Daryl H Allred

发明人： John G Rohrbaugh ,  Jeff Rearick ,  Daryl H Allred

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model. The model is simplified by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block is a circuit block desired in the computer assisted analysis and if so keeping the circuit block as part of the simplified hierarchical circuit model; and by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block comprises a parent circuit block containing a child circuit block desired in the computer assisted analysis and if so keeping the parent circuit block as part of the simplified hierarchical circuit model.

摘要翻译： 一种在分层电路模型上执行计算机辅助分析功能的方法和装置。 该方法是通过输入层次化电路模型，指定层级内的至少一个电路块作为目标块上的功能的目标，并通过删除不影响分析功能的电路块来简化分级电路模型，以产生 一个简化的分层电路模型。 然后可以在简化的分层电路模型上执行计算机辅助分析功能。 通过对分层电路模型进行块分析来简化模型，以确定电路块是否是计算机辅助分析中期望的电路块，并且如果将电路块保持为简化分层电路模型的一部分; 并且通过对分级电路模型进行块分析以确定电路块是否包括包含计算机辅助分析中期望的子电路块的父电路块，以及如果保持母电路块作为简化分级的一部分 电路模型。

公开(公告)号：US06865706B1

公开(公告)日：2005-03-08

申请号：US09589338

申请日：2000-06-07

申请人： John G Rohrbaugh ,  Jeff Rearick

发明人： John G Rohrbaugh ,  Jeff Rearick

IPC分类号： G01R31/3183 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318371 ,  G01R31/318342

摘要： The present invention is generally directed to an improved automatic test pattern generator for generating test patterns that are used by an integrated circuit testing device. In accordance with one aspect of the invention, a method is provided for generating a set of test vectors for testing an integrated circuit, each test vector of the set of test vectors containing a plurality of bits defining test inputs for the integrated circuit. The method includes the steps of defining a list of faults for the integrated circuit, and generating at least one test vector that defines values for those inputs necessary to detect at least one target fault selected from the list of faults, the values comprising only a portion of the bits of the at least one test vector, wherein a remainder of the bits in the at least one test vector are unspecified bit positions. The method further includes the step of setting the values of a plurality of the unspecified bit positions using a non-random filling methodology.

摘要翻译： 本发明一般涉及用于产生由集成电路测试装置使用的测试图案的改进的自动测试图案发生器。 根据本发明的一个方面，提供了一种用于生成用于测试集成电路的测试矢量的集合的方法，该组测试矢量的每个测试矢量包含多个定义用于集成电路的测试输入的位。 该方法包括以下步骤：定义集成电路的故障列表，以及生成至少一个测试向量，该测试向量定义用于检测从故障列表中选择的至少一个目标故障所必需的那些输入的值，该值仅包括一部分 的至少一个测试向量的比特，其中所述至少一个测试向量中的剩余比特是未指定的比特位置。 该方法还包括使用非随机填充方法来设置多个未指定比特位置的值的步骤。

公开(公告)号：US06653957B1

公开(公告)日：2003-11-25

申请号：US10266283

申请日：2002-10-08

申请人： Sylvia Patterson ,  Jeff Rearick

发明人： Sylvia Patterson ,  Jeff Rearick

IPC分类号： H03M1300

CPC分类号： G01R31/31715 ,  G01R31/2853 ,  G01R31/31855 ,  G01R31/3187 ,  G11C29/48 ,  G11C2029/3202

摘要： Improvement in the transmission of Boundary Scan Test mode data may be achieved through the assignment of boundary scan test mode traffic to selected bit patterns that facilitate clock recovery and frame alignment in the serial channel. The encoding of boundary scan test traffic as such may be achieved through either multiplexed transmission to the serializer/deserializer (SERDES) alongside a regular channel encoder or incorporated into the channel encoder.

摘要翻译： 边界扫描测试模式数据传输的改进可以通过将边界扫描测试模式流量分配给便于串行通道中的时钟恢复和帧对准的所选位模式来实现。 边界扫描测试业务的编码本身可以通过与常规信道编码器一起复用到串行器/解串器（SERDES）或并入到信道编码器中来实现。

公开(公告)号：US5905986A

公开(公告)日：1999-05-18

申请号：US779760

申请日：1997-01-07

申请人： John G Rohrbaugh ,  Jeff Rearick

发明人： John G Rohrbaugh ,  Jeff Rearick

IPC分类号： G11C29/10 ,  G06F17/30

CPC分类号： G11C29/56004 ,  G11C29/10 ,  Y10S707/99942

摘要： A method for more efficient handling of data used in testing electronic integrated circuits and boards consisting of specifying data in a flat tabular format. Signal data are contained in columns and cycle data are contained in rows. Any given signal in a cycle will typically be a "0" or "1". If a signal does not change from one cycle to the next, the character "0" or "1" is replaced in the latter cycle by the dot "." character. As a result of the "." character replacements, the data is much more highly compressible by standard compression software than before, thus requiring less storage space for the data.

摘要翻译： 一种用于更有效地处理用于测试电子集成电路和电路板的数据的方法，包括以扁平表格格式指定数据。 信号数据包含在列中，循环数据包含在行中。 一个循环中的任何给定信号一般为“0”或“1”。 如果信号没有从一个周期改变到下一个周期，字符“0”或“1”在后一个周期中被替换为“”。 字符。 由于“。” 字符替换，数据通过标准压缩软件比以前更高度可压缩，因此需要较少的数据存储空间。