公开(公告)号：US06309930B1

公开(公告)日：2001-10-30

申请号：US09708636

申请日：2000-11-09

申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

IPC分类号： H01L21336

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.

摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。 诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。 存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由 通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。 触点（K5）同时接触MOS晶体管的多个部分。

公开(公告)号：US06222753B1

公开(公告)日：2001-04-24

申请号：US09446419

申请日：1999-12-20

申请人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

发明人： Bernd Goebel ,  Emmerich Bertagnolli ,  Josef Willer ,  Barbara Hasler ,  Paul-Werner von Basse

IPC分类号： G11C700

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

摘要翻译： 每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。 存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。 存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置 相对于垂直于表面的轴部分地布置在不同高度的导电结构。 触头同时接触MOS晶体管的多个部分。

公开(公告)号：US6118159A

公开(公告)日：2000-09-12

申请号：US259376

申请日：1999-02-26

申请人： Josef Willer ,  Franz Hofmann ,  Hans Reisinger ,  Emmerich Bertagnolli ,  Bernd Gobel ,  Barbara Hasler ,  Karl-Heinz Tietgen

发明人： Josef Willer ,  Franz Hofmann ,  Hans Reisinger ,  Emmerich Bertagnolli ,  Bernd Gobel ,  Barbara Hasler ,  Karl-Heinz Tietgen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.

摘要翻译： 存储单元配置包括以NOR架构连接的垂直晶体管。 垂直晶体管设置在沟槽的侧面。 每个垂直晶体管包括电绝缘浮栅，其电荷可以由于控制栅极电极和源极/漏极区域之间的压降而由Fowler-Nordheim隧穿而改变。 为了降低工作电压，与控制栅电极和浮置栅电极之间的通道宽度平行的方向上的耦合区域的长度小于沟道宽度。 这是通过沟槽侧面部分的热氧化实现的。 在横向于沟槽的方向上相邻的晶体管共享位线。 每个位线具有轻掺杂的第一部分和高度掺杂的第二部分。 通过使用由间隔物延伸的带状掩模，可以进一步扩大耦合面积。

公开(公告)号：US06642565B2

公开(公告)日：2003-11-04

申请号：US09935624

申请日：2001-08-23

申请人： Emmerich Bertagnolli ,  Till Schlösser ,  Josef Willer

发明人： Emmerich Bertagnolli ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L28/82

摘要： A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

公开(公告)号：US06403440B1

公开(公告)日：2002-06-11

申请号：US09285897

申请日：1999-04-08

申请人： Emmerich Bertagnolli ,  Josef Willer

发明人： Emmerich Bertagnolli ,  Josef Willer

IPC分类号： H01L2120

CPC分类号： H01L28/87 ,  H01L27/10852 ,  H01L28/88

摘要： A method for fabricating a stacked capacitor in a semiconductor configuration, in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The semiconductor configuration having one electrode of a stacked capacitor produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. After the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed, with the result that the electrode has the same conductivity type as the terminal region and no pn junction occurs between the electrode and terminal region.

摘要翻译： 一种用于制造半导体构造的层叠电容器的方法，其中层叠电容器的一个电极经由第一导电类型的端子区域连接到晶体管的源极或漏极。 半导体结构具有通过利用掺杂到不同程度的第二导电类型的半导体层的不同蚀刻速率而产生的堆叠电容器的一个电极。 在层叠电容器的一个电极的蚀刻之后，执行在蚀刻操作之后保留的半导体层的掺杂反转到第一导电类型，结果是电极具有与端子区域相同的导电类型，并且没有pn结 发生在电极和端子区域之间。

公开(公告)号：US06586795B2

公开(公告)日：2003-07-01

申请号：US09873659

申请日：2001-06-04

申请人： Bernd Goebel ,  Emmerich Bertagnolli

发明人： Bernd Goebel ,  Emmerich Bertagnolli

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841

摘要： Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches. Above the recess, an insulating structure is preferably disposed in the first indentation and adjoins two adjacent ones of the insulation trenches.

摘要翻译： 每个存储单元包括一个晶体管和一个电容器。 电容器的存储节点设置在第一压痕中，而晶体管的栅电极设置在第二压痕中。 晶体管的上源极/漏极区域，沟道区域和下部源极/漏极区域彼此并排设置，并且每个与第一压痕的第一侧面和第二压痕相邻。 第一侧面的至少一部分设置有电容器电介质，其在下源极/漏极区域的区域中具有凹槽，其中存储器节点邻接下部源极/漏极区域。 存储器单元中的第一个存储单元的第二缩进可以与布置在第二个存储单元的第一个凹槽中的存储器节点相邻。 第二个凹痕可以是横向延伸到绝缘沟槽的字线沟槽的部分。 在凹部上方，绝缘结构优选设置在第一压痕中，并与两个绝缘沟槽相邻。

公开(公告)号：US06566202B2

公开(公告)日：2003-05-20

申请号：US10081902

申请日：2002-02-22

申请人： Bernd Goebel ,  Emmerich Bertagnolli

发明人： Bernd Goebel ,  Emmerich Bertagnolli

IPC分类号： H01L2100

CPC分类号： H01L21/823885 ,  H01L27/092

摘要： An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

公开(公告)号：US6097049A

公开(公告)日：2000-08-01

申请号：US272077

申请日：1999-03-18

申请人： Bernd Goebel ,  Eve Marie Martin ,  Emmerich Bertagnolli

发明人： Bernd Goebel ,  Eve Marie Martin ,  Emmerich Bertagnolli

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/10823 ,  H01L27/10876 ,  Y10S257/906 ,  Y10S257/907

摘要： A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines. A second source/drain zone of the selection transistor is buried in the substrate and, for example, is part of a doped layer or of a grid-shaped doped region or is connected to the substrate via a buried contact. A memory cell can be manufactured given open bit lines as well as given folded bit lines, wherein it is manufactured with an area of 4F.sup.2.

摘要翻译： 一种DRAM单元布置及其制造方法，其中存储电容器经由垂直选择晶体管的第一源极/漏极区域和位线连接。 由于存储电容器和位线布置在基板的大致上方，所以位线可以由具有高导电性的材料制造，并且具有高介电常数的材料可用于存储电容器。 至少第一源极/漏极区域和沟道区域是由至少两个侧壁横向限制的突起状半导体结构的部分。 相应的字线可以布置在两个侧壁处。 阻止由该字线驱动选择晶体管的元件被布置在通道区域和一条字线之间。 选择晶体管的第二源极/漏极区域被掩埋在衬底中，并且例如是掺杂层或栅格形掺杂区域的一部分，或者通过埋入触点连接到衬底。 可以制造给定的开放位线以及给定的折叠位线的存储器单元，其中制造的面积为4F2。

公开(公告)号：US6075265A

公开(公告)日：2000-06-13

申请号：US105235

申请日：1998-06-26

申请人： Bernd Goebel ,  Emmerich Bertagnolli

发明人： Bernd Goebel ,  Emmerich Bertagnolli

IPC分类号： G11C11/34 ,  G11C11/405 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/10852

摘要： The DRAM cell arrangement has three transistors per memory cell, at least one of which transistors is designed as a vertical transistor. The transistors may be formed on sidewalls (1F1, 1F2, 2F2) of trenches (G1, G2). In order to fabricate contact regions (K) which respectively connect together three source/drain regions (1 S/D1, 3 S/D2, 2 S/D 2) of different transistors, it is advantageous to arrange the trenches (G1, G2) alternately with a larger distance and a smaller distance from one another. Gate electrodes (Ga1, Ga3) of transistors may be formed as parts of writing word lines (WS) or read-out word lines (WA) in the form of spacers on sidewalls (1F1, 1F2) of the trenches (G1). Connections between gate electrodes (Ga2) and source/drain regions (3 S/D1) may be made via conductive structures (L).

摘要翻译： 每个存储单元DRAM单元布置具有三个晶体管，其中至少一个晶体管被设计为垂直晶体管。 晶体管可以形成在沟槽（G1，G2）的侧壁（1F1,1F2,2F2）上。 为了制造分别连接不同晶体管的三个源极/漏极区域（1S / D1,3S / D2,2S / D 2）的接触区域（K），有利的是将沟槽（G1，G2） ）交替地具有较大的距离和彼此较小的距离。 晶体管的栅电极（Ga1，Ga3）可以形成为在沟槽（G1）的侧壁（1F1,1F2）上的间隔物形式的写入字线（WS）或读出字线（WA）的部分。 栅电极（Ga2）和源/漏区（3S / D1）之间的连接可以通过导电结构（L）制成。

公开(公告)号：US06352894B1

公开(公告)日：2002-03-05

申请号：US09482064

申请日：2000-01-13

申请人： Bernd Goebel ,  Wolfgang Roesner ,  Franz Hofmann ,  Emmerich Bertagnolli ,  Eve Marie Martin

发明人： Bernd Goebel ,  Wolfgang Roesner ,  Franz Hofmann ,  Emmerich Bertagnolli ,  Eve Marie Martin

IPC分类号： H01L218242

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  Y10S257/906 ,  Y10S438/947

摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.

摘要翻译： 存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。 每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。 存储电容器连接在第一源极/漏极区域和位线之间。 位线以及存储电容器基本上布置在半导体衬底的上方。 选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。 字线可以形成为相邻栅电极的形式自对称。 可以通过仅使用一个掩模的蚀刻来产生突起。 可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。