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    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    1.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20070211933A1

    公开(公告)日：2007-09-13

    申请号：US11748575

    申请日：2007-05-15

    申请人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    3.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20050094863A1

    公开(公告)日：2005-05-05

    申请号：US10605849

    申请日：2003-10-30

    申请人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00 ,  G06T7/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    Method and system using the design pattern of IC chips in the processing thereof
    9.
    发明授权
    Method and system using the design pattern of IC chips in the processing thereof 失效
    在处理IC芯片的设计模式的方法和系统

    公开(公告)号：US5552996A

    公开(公告)日：1996-09-03

    申请号：US390392

    申请日：1995-02-16

    申请人： Cheryl A. Hoffman ,  Mark A. Lavin ,  William Leipold ,  Kathleen McGroddy ,  Daniel J. Nickel

    发明人： Cheryl A. Hoffman ,  Mark A. Lavin ,  William Leipold ,  Kathleen McGroddy ,  Daniel J. Nickel

    IPC分类号： B24B37/04 ,  B24B49/00 ,  H01L21/66 ,  G06F19/00

    CPC分类号： B24B37/005 ,  B24B37/042 ,  B24B49/00 ,  H01L22/20 ,  Y10S438/941

    摘要： The techniques of the present invention facilitate the control of an IC chip fabrication level of a fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.

    摘要翻译： 本发明的技术有助于基于正在制造的IC芯片的设计图案来控制制造工艺的IC芯片制造水平。 具有多个部分的网格被施加在IC芯片的制造级别的设计图案上。 然后，为网格的每个部分中包含的设计模式自动建立模式密度值。 然后基于图案密度值来控制IC芯片制造水平。 例如，建立的图案密度值有助于自动确定CMP工艺停止参数，或者通过IC芯片的设计图案上的图案密度差导致的蚀刻速率变化的自动补偿。

    AUTONOMIC GRAPHICAL PARTITIONING
    10.
    发明申请
    AUTONOMIC GRAPHICAL PARTITIONING 失效
    自动图像分割

    公开(公告)号：US20050125756A1

    公开(公告)日：2005-06-09

    申请号：US10707286

    申请日：2003-12-03

    申请人： Gary Ditlow ,  Daria Dooling ,  Timothy Dunham ,  William Leipold ,  Stephen Thomas ,  Ralph Williams

    发明人： Gary Ditlow ,  Daria Dooling ,  Timothy Dunham ,  William Leipold ,  Stephen Thomas ,  Ralph Williams

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5072

    摘要： Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

    摘要翻译： 公开了通过基于设计层级中的逻辑宏的大小启发式来识别集成电路设计中的逻辑块来分割集成电路设计的方法和结构。 本发明确定逻辑块的数量是否在期望数量的逻辑块的范围内，并重复识别用于集成电路设计的不同层级的逻辑块的处理，直到逻辑块的数量在所需数量的范围内 的逻辑块。 这作为分配芯片的指南，而不是格栅分割。