公开(公告)号：US5552996A

公开(公告)日：1996-09-03

申请号：US390392

申请日：1995-02-16

申请人： Cheryl A. Hoffman ,  Mark A. Lavin ,  William Leipold ,  Kathleen McGroddy ,  Daniel J. Nickel

发明人： Cheryl A. Hoffman ,  Mark A. Lavin ,  William Leipold ,  Kathleen McGroddy ,  Daniel J. Nickel

IPC分类号： B24B37/04 ,  B24B49/00 ,  H01L21/66 ,  G06F19/00

CPC分类号： B24B37/005 ,  B24B37/042 ,  B24B49/00 ,  H01L22/20 ,  Y10S438/941

摘要： The techniques of the present invention facilitate the control of an IC chip fabrication level of a fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.

摘要翻译： 本发明的技术有助于基于正在制造的IC芯片的设计图案来控制制造工艺的IC芯片制造水平。 具有多个部分的网格被施加在IC芯片的制造级别的设计图案上。 然后，为网格的每个部分中包含的设计模式自动建立模式密度值。 然后基于图案密度值来控制IC芯片制造水平。 例如，建立的图案密度值有助于自动确定CMP工艺停止参数，或者通过IC芯片的设计图案上的图案密度差导致的蚀刻速率变化的自动补偿。

公开(公告)号：US4999815A

公开(公告)日：1991-03-12

申请号：US479137

申请日：1990-02-13

申请人： John E. Barth, Jr. ,  Charles E. Drake ,  William P. Hovis ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Scott C. Lewis ,  Daniel J. Nickel ,  James A. Yankosky

发明人： John E. Barth, Jr. ,  Charles E. Drake ,  William P. Hovis ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Scott C. Lewis ,  Daniel J. Nickel ,  James A. Yankosky

IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406

CPC分类号： G11C8/18 ,  G11C8/10 ,  G11C8/12

摘要： Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.

公开(公告)号：US5134616A

公开(公告)日：1992-07-28

申请号：US479145

申请日：1990-02-13

申请人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

发明人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

IPC分类号： G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/84 ,  G06F11/1008

摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：US07135255B2

公开(公告)日：2006-11-14

申请号：US10249317

申请日：2003-03-31

申请人： Scott J. Bukofsky ,  John K. DeBrosse ,  Marco Hug ,  Lars W. Liebmann ,  Daniel J. Nickel ,  Juergen Preuninger

发明人： Scott J. Bukofsky ,  John K. DeBrosse ,  Marco Hug ,  Lars W. Liebmann ,  Daniel J. Nickel ,  Juergen Preuninger

IPC分类号： G01F9/00

CPC分类号： G03F1/30

摘要： A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

摘要翻译： 减少关键特征而不改变布局尺寸的线端缩短的相移掩模形状增加了所需的相移规则。 相位特征给出一个有角度的延伸，其包括光刻缩短值。 这允许将临界形状设计得更接近参考层，然后它可以没有成角度的延伸特征。 通过沿着非临界部分延长特征，显着减少了给定装置段之外的相位掩模延伸特征; 将特征参考点移动到设备层; 并且将相延伸特征沿着装置段的非关键部分平坦化为L形或T形。 应用这些设计规则允许在当前条件下绘制栅极导体，并将相位形状置于内部，而不会将栅极导体尺寸延伸到下一个特征。

公开(公告)号：US6086627A

公开(公告)日：2000-07-11

申请号：US15825

申请日：1998-01-29

申请人： Roy S. Bass, Jr. ,  Daniel J. Nickel ,  Daniel C. Sullivan ,  Steven H. Voldman

发明人： Roy S. Bass, Jr. ,  Daniel J. Nickel ,  Daniel C. Sullivan ,  Steven H. Voldman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A integrated circuit (IC) chip with ESD protection level and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and array pads are wired to I/O cells located on the chip. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection level. The design is then verified by first identifying the chip pads, I/O cells and ESD protect devices. Connections between these three structures are verified. Wires between the ESD protect devices and the chip pads and I/O cells are shrunk such that unsuitable connections becomes opens (disconnected) and are found in subsequent checking. Finally connections to guard rings are checked. Power rails are checked in a similar manner.

摘要翻译： 具有ESD保护等级的集成电路（IC）芯片，以及IC芯片接线的系统和方法。 每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。 这些约束被传播到设计，并且阵列焊盘被连接到位于芯片上的I / O单元。 因此，布线使得ESD保护器件的导线和通孔足够宽以提供足够的ESD保护等级。 然后通过首先识别芯片焊盘，I / O单元和ESD保护器件来验证该设计。 验证这三个结构之间的连接。 ESD保护器件与芯片焊盘和I / O单元之间的电线会收缩，使得不合适的连接变得断开（断开），并在随后的检查中找到。 最后检查与保护环的连接。 以类似的方式检查电源轨。

公开(公告)号：US07093212B2

公开(公告)日：2006-08-15

申请号：US10708820

申请日：2004-03-26

申请人： William F. DeCamp ,  Daniel J. Nickel

发明人： William F. DeCamp ,  Daniel J. Nickel

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A system, method and program product for performing density checking of an IC design. The invention establishes an evaluation array for the IC design including an array element for each evaluation window of the IC design. The number of evaluation windows is based on a smallest necessary granularity. A single pass through shape data for the IC design is then conducted to populate each array element with a shape area for a corresponding evaluation window. Density checking is performed by iterating over the evaluation array using a sub-array. The sub-array may have the size of the preferred density design rule window. The invention removes the need for repetitive calculations, and results in a more efficient approach to density checking.

摘要翻译： 一种用于执行IC设计的密度检查的系统，方法和程序产品。 本发明建立了用于IC设计的评估阵列，其包括用于IC设计的每个评估窗口的阵列元件。 评估窗口的数量基于最小的必要粒度。 然后对IC设计进行单次通过形状数据，以便为每个阵列元素填充相应评估窗口的形状区域。 通过使用子数组迭代评估数组来执行密度检查。 子阵列可以具有优选密度设计规则窗口的大小。 本发明消除了对重复计算的需要，并且导致了更有效的密度检查方法。