公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06292399B1

公开(公告)日：2001-09-18

申请号：US09609897

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

摘要翻译： 提供控制电路和在读操作模式期间为半导体存储器件中的选定存储核心单元产生准确的漏极电压的方法。 提供选择栅极晶体管，其导通路径耦合在所选存储核心单元之一的电源电压和漏极之间。 差分放大器电路响应于对应于所选择的存储器单元的漏极电压的位线电压和用于产生选择栅极电压的参考电压。 当位线电压高于目标电压时，选择栅极电压降低，并且当位线电压低于目标电压时，选择栅极电压增加。 源极跟随器电路响应选择栅极电压以产生保持在目标电压的位线电压。 选择栅极晶体管的控制栅极被连接以接收选择栅极电压，以将所选择的存储器核心单元的漏极处的电压保持为大致恒定。

公开(公告)号：US6081455A

公开(公告)日：2000-06-27

申请号：US232023

申请日：1999-01-14

申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12 ,  G11C16/00

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12

摘要： A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

摘要翻译： 块解码器包括p阱。 低电压源耦合到p阱，用于断定对p阱的体偏置电压。 n型字线传输晶体管位于p阱内并耦合到字线，用于将编程电压传递到字线。 耦合高电压源以通过配置成断定传输晶体管的栅极上的电压的电路。 低电压源被配置为在编程期间向p阱施加大约10伏特或更高的电压，从而降低位于p内的NMOS晶体管的源极和体区之间的电压（以及阈值电压） -好。 因此，需要施加到传输晶体管的电压量减小。 此外，通过电路可以用于较低的电源电压，因为电源电压受p阱内n型晶体管的阈值电压的限制。

公开(公告)号：US6009014A

公开(公告)日：1999-12-28

申请号：US90296

申请日：1998-06-03

申请人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

发明人： Shane C. Hollmer ,  Chung-You Hu ,  Binh Q. Le ,  Pau-ling Chen ,  Jonathan Su ,  Ravi Gutala ,  Colin Bill

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/344

摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

摘要翻译： 本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压 在擦除验证期间每个晶体管的控制栅极。 偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。 如果所有晶体管都不被擦除，则执行另一个擦除操作。 重复擦除直到擦除验证操作指示所有晶体管被正确擦除。 通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

公开(公告)号：US06424570B1

公开(公告)日：2002-07-23

申请号：US09892189

申请日：2001-06-26

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： H02M3/073

摘要： A system is described for generating a charge pump voltage for flash memory operations, wherein a supply voltage detection circuit (e.g., analog to digital converter, digital thermometer) is configured to detect a supply voltage value and generate one or more supply voltage level detection signals associated therewith. The system further includes a charge pump circuit comprising one or more stages operable to receive a supply voltage and generate the charge pump output voltage having a value greater than the supply voltage, and a charge pump compensation circuit operably coupled to the supply voltage detection circuit and the charge pump circuit. The charge pump compensation circuit is operable to receive the one or more output signals from the supply voltage detection circuit and modulate a capacitive loading associated with the charge pump circuit based on the one or more output signals, thereby creating an improved low power charge pump which uses a modulated pumping capacitance to compensate for fluctuations of the input power supply (for example, VCC), to produce a slow ripple and low noise output which may be used as a pumped voltage for various mode operations (e.g., erase, program modes) of memory cells.

摘要翻译： 描述了一种用于产生用于闪速存储器操作的电荷泵电压的系统，其中电源电压检测电路（例如，模数转换器，数字温度计）被配置为检测电源电压值并产生一个或多个电源电压电平检测信号 相关联。 该系统还包括电荷泵电路，其包括一个或多个级，可操作以接收电源电压并产生具有大于电源电压的值的电荷泵输出电压;以及电荷泵补偿电路，其可操作地耦合到电源电压检测电路和 电荷泵电路。 电荷泵补偿电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于该一个或多个输出信号调制与电荷泵电路相关联的电容性负载，从而产生改进的低功率电荷泵， 使用调制的泵浦电容来补偿输入电源的波动（例如VCC），以产生慢波纹和低噪声输出，其可用作用于各种模式操作（例如擦除，编程模式）的泵浦电压， 的记忆细胞。

公开(公告)号：US06208561B1

公开(公告)日：2001-03-27

申请号：US09593303

申请日：2000-06-13

申请人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/08

摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

摘要翻译： 提供了一种用于降低闪存X解码器中的电容负载以便精确地将电压控制为选择的字线和块选择线的装置和方法。 解码结构分别将第一升压电压施加到字线N阱区域，并将第二升压电压施加到所选择的字线，以便由于与字线N阱区域相关联的重电容性负载而减小所选字线上的容性负载。 解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载， 井区。 因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。

公开(公告)号：US06137153A

公开(公告)日：2000-10-24

申请号：US23497

申请日：1998-02-13

申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

IPC分类号： H01L29/788 ,  H01L29/94 ,  H01L29/00

CPC分类号： H01L29/94 ,  H01L29/7881

摘要： A capacitor structure which exhibits a constant capacitance at non-negative voltages is provided by erasing a P-well floating gate NMOS transistor prior to its use as a capacitor. By erasing the transistor, a negative threshold voltage is obtained, thereby turning on the transistor and placing the transistor in an inversion state where the MOS capacitance is voltage-independent. Such transistors can be utilized as capacitors, whereby one plate of the capacitor corresponds to the control gate of the transistor and the other plate corresponds to the commonly connected source, drain, P-well, and deep N-well regions of the transistor, in voltage regulator circuits or other circuits in which node stabilization is desired. As a result, the capacitance is constant even at initialization when zero volts is applied.

摘要翻译： 在非负电压下呈现恒定电容的电容器结构通过在用作电容器之前擦除P阱浮置NMOS NMOS晶体管来提供。 通过擦除晶体管，获得负阈值电压，从而导通晶体管并将晶体管置于MOS电容与电压无关的反转状态。 这种晶体管可以用作电容器，由此电容器的一个板对应于晶体管的控制栅极，另一个板对应于晶体管的公共连接的源极，漏极，P阱和深N阱区域，其中 电压调节器电路或其中需要节点稳定的其他电路。 结果，即使在施加零伏特的初始化时，电容也是恒定的。

公开(公告)号：US5638326A

公开(公告)日：1997-06-10

申请号：US630919

申请日：1996-04-05

申请人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

发明人： Shane C. Hollmer ,  Pau-Ling Chen ,  Binh Q. Le

IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.

摘要翻译： 包括具有偏置电路的页缓冲器和参考阵列的闪速存储器，其能够使用页缓冲器并行读取和验证存储单元的字线上的值，而与温度，Vcc和工艺变化无关。 偏置电路包括具有连接到参考单元阵列的源的共源共栅晶体管，其提供单个参考信号。 偏置共源共栅将参考信号耦合到偏置发生器中的偏置反相器的输入，而偏置发生器中的偏置负载晶体管将Vcc耦合到偏置反相器输入。 页面缓冲器包括一组锁存器，每个锁存器通过级联耦合到存储器单元。 每个锁存器中的第一个反相器具有与偏置反相器中的晶体管尺寸匹配的晶体管。 锁存器负载晶体管连接在每个锁存器中的第二反相器的上拉和下拉晶体管之间，并且其大小适于匹配偏置负载晶体管。 偏置负载晶体管和锁存负载晶体管的栅极都耦合到偏置反相器的输出，使得每个锁存器的第一反相器具有镜像偏置反相器的输入的输入。

公开(公告)号：US06292406B1

公开(公告)日：2001-09-18

申请号：US09609678

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/30

摘要： Control circuitry and a method for generating an accurate boosted wordline voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Memory core transistors are provided which have their conduction path being coupled between a power supply voltage and a ground potential. Differential amplifier circuitry is responsive to a boost signal and a reference voltage for generating a select wordline voltage. The select wordline voltage is decreased when the wordline voltage is higher than a desired voltage and is increased when the wordline voltage is lower than the desired voltage. The control gates of the memory core transistors are responsive to the select wordline voltage.

摘要翻译： 提供了控制电路和用于在读操作模式期间为半导体存储器件中的所选择的存储器核心单元产生精确提升的字线电压的方法。 提供存储芯体晶体管，其导通路径耦合在电源电压和地电位之间。 差分放大器电路响应于升压信号和用于产生选择字线电压的参考电压。 当字线电压高于期望电压时，选择字线电压降低，当字线电压低于期望电压时，选择字线电压降低。 存储核心晶体管的控制栅极响应于选择字线电压。

公开(公告)号：US5978266A

公开(公告)日：1999-11-02

申请号：US24880

申请日：1998-02-17

申请人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

发明人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.

摘要翻译： 提供了一种用于在编程期间偏置NAND阵列EEPROM以允许阵列在进入穿透之前被进一步缩小的方法。 NAND阵列的接地选择晶体管的源极被偏置为Vcc而不是接地，以减小接地选择晶体管的源极和漏极两端的电压降。 结果，在获得穿通之前，可以进一步缩短接地选择晶体管的沟道长度，从而产生更高密度的EEPROM。