公开(公告)号：US08051313B2

公开(公告)日：2011-11-01

申请号：US12110589

申请日：2008-04-28

申请人： Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

发明人： Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

IPC分类号： G06F1/00 ,  G05F1/10 ,  H03K3/02 ,  H03K17/16

CPC分类号： H03K3/0375

摘要： An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

摘要翻译： 用于在电力域中异步降低功率的装置，系统和方法。 在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的 状态保持信号和肯定状态隔离信号。 在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

公开(公告)号：US20090267638A1

公开(公告)日：2009-10-29

申请号：US12110589

申请日：2008-04-28

申请人： Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

发明人： Bixia Li ,  Hugh Mair ,  Minh Chau ,  Alice Wang ,  Uming Ko

IPC分类号： H03K19/003 ,  H03K3/02

CPC分类号： H03K3/0375

摘要： An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

摘要翻译： 用于在电力域中异步降低功率的装置，系统和方法。 在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的 状态保持信号和肯定状态隔离信号。 在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

公开(公告)号：US20080307240A1

公开(公告)日：2008-12-11

申请号：US11760263

申请日：2007-06-08

申请人： Franck Dahan ,  Gilles Dubost ,  Gordon Gammie ,  Uming Ko ,  Hugh Mair ,  Sang-Won Song ,  Alice Wang ,  William D. Wilson

发明人： Franck Dahan ,  Gilles Dubost ,  Gordon Gammie ,  Uming Ko ,  Hugh Mair ,  Sang-Won Song ,  Alice Wang ,  William D. Wilson

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F21/79 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).

摘要翻译： 一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作 功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路 功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

公开(公告)号：US20100103760A1

公开(公告)日：2010-04-29

申请号：US12258747

申请日：2008-10-27

申请人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

发明人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/147

摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

摘要翻译： 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US20070223294A1

公开(公告)日：2007-09-27

申请号：US11385151

申请日：2006-03-21

申请人： Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

发明人： Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

IPC分类号： G11C7/00

CPC分类号： G11C8/10

摘要： A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

摘要翻译： 一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。 存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。 控制逻辑向存储器提供目标位单元的地址。 在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

公开(公告)号：US20110216619A1

公开(公告)日：2011-09-08

申请号：US13106612

申请日：2011-05-12

申请人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

发明人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

摘要翻译： 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US20090039952A1

公开(公告)日：2009-02-12

申请号：US11947012

申请日：2007-11-29

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以定义自动功率选通电源域中的单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US07920020B2

公开(公告)日：2011-04-05

申请号：US12814195

申请日：2010-06-11

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US07760011B2

公开(公告)日：2010-07-20

申请号：US11947012

申请日：2007-11-29

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US10275010B2

公开(公告)日：2019-04-30

申请号：US15119731

申请日：2015-02-16

申请人： MediaTek Singapore Pte. Ltd. ,  Hugh Thomas Mair ,  Sumanth Katte Gururajarao ,  Gordon Gammie ,  Alice Wang ,  Uming Ko ,  Rolf Lagerquist

发明人： Hugh Thomas Mair ,  Sumanth Katte Gururajarao ,  Gordon Gammie ,  Alice Wang ,  Uming Ko ,  Rolf Lagerquist

IPC分类号： G06F1/32 ,  G06F1/324 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3296

摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.