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公开(公告)号：US10115527B2
公开(公告)日：2018-10-30
申请号：US14642222
申请日：2015-03-09
申请人： BlackBerry Limited
摘要： A system that incorporates teachings of the subject disclosure may include, for example, a fabricated thin film capacitor formed by depositing a first dielectric layer on a first electrode layer utilizing a first process that is performed at a first temperature, depositing a second dielectric layer on the first dielectric layer utilizing a second process that forms a randomly-oriented grain structure for the second dielectric layer, depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a second temperature and that forms a columnar-oriented grain structure for the third dielectric layer where the second temperature is higher than the first temperature, and depositing a second electrode layer on the third dielectric layer to form the thin film capacitor. Other embodiments are disclosed.
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公开(公告)号：US20160268048A1
公开(公告)日：2016-09-15
申请号：US14642222
申请日：2015-03-09
申请人： BlackBerry Limited
CPC分类号： H01G4/33 , H01G4/012 , H01G4/1227 , H01L28/56
摘要： A system that incorporates teachings of the subject disclosure may include, for example, a fabricated thin film capacitor formed by depositing a first dielectric layer on a first electrode layer utilizing a first process that is performed at a first temperature, depositing a second dielectric layer on the first dielectric layer utilizing a second process that forms a randomly-oriented grain structure for the second dielectric layer, depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a second temperature and that forms a columnar-oriented grain structure for the third dielectric layer where the second temperature is higher than the first temperature, and depositing a second electrode layer on the third dielectric layer to form the thin film capacitor. Other embodiments are disclosed.
摘要翻译： 结合本公开的教导的系统可以包括例如通过在第一电极层上沉积第一电介质层而形成的制造的薄膜电容器，所述第一电介质层利用在第一温度下执行的第一工艺，将第二电介质层沉积在 所述第一电介质层利用形成用于所述第二电介质层的随机取向的晶粒结构的第二工艺，利用在第二温度下进行的第三工艺，在所述第二电介质层上沉积第三电介质层，并形成柱状取向 晶体结构，其中所述第二温度高于所述第一温度，以及在所述第三电介质层上沉积第二电极层以形成所述薄膜电容器。 公开了其他实施例。
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公开(公告)号：US09318266B2
公开(公告)日：2016-04-19
申请号：US14190353
申请日：2014-02-26
申请人： BlackBerry Limited
CPC分类号： H01G5/38 , H01G7/02 , H01G7/06 , H01L27/016 , H01L27/0808 , H01L28/60
摘要： A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.
摘要翻译： 多层电容器包括三个或更多个电容器层。 第一层包括第一DC偏置可调电容器。 声耦合到第一层的第二层包括第二DC偏置的可调电容器。 声耦合到第二层的第三层包括第三直流偏置可调电容器。 第一，第二和第三电容器的每个电介质具有在5％以内约相同频率的共振，并且第一，第二和第三电容器的内部电极具有大约相同频率的共振，在5％以内。 每个层的共振至少是厚度，密度和材料的函数。 第一，第二和第三层被偏置以产生破坏性声学干扰，并且多层电容器可在大于0.1GHz的频率下操作。
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4.发明授权Method of forming a target for deposition of doped dielectric films by sputtering 有权通过溅射形成用于沉积掺杂介电膜的靶的方法公开(公告)号：US09404175B2
公开(公告)日：2016-08-02
申请号：US13757999
申请日：2013-02-04
申请人： BLACKBERRY Limited
CPC分类号： C23C14/3414 , C23C14/083
摘要： A system that incorporates teachings of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents to provide a powder of constituents. Other embodiments are disclosed.
摘要翻译： 结合本公开的教导的系统可以包括例如对第一主要成分，第二主要成分和用于形成所需材料的次要成分进行选择的方法。 该方法可以包括在单一混合步骤中混合第一主要成分，第二主要成分和次要成分以提供成分的混合物。 该方法可以包括干燥组分的混合物以提供组分的干燥混合物并煅烧干燥的组分混合物以提供组分的煅烧混合物。 该方法可包括加工煅烧的组分混合物以提供成分粉末。 公开了其他实施例。
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公开(公告)号：US20200066836A1
公开(公告)日：2020-02-27
申请号：US16672151
申请日：2019-11-01
申请人： BlackBerry Limited
IPC分类号： H01L49/02 , H01L23/528 , H01L21/3213 , H01L21/311 , H01L21/283 , H01L23/522 , H01G7/06 , H01G4/12 , H01G4/33
摘要： A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
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6.发明申请公开(公告)号：US20190272956A1
公开(公告)日：2019-09-05
申请号：US16409188
申请日：2019-05-10
申请人： BlackBerry Limited
IPC分类号： H01G7/06 , H01L49/02 , H01L23/522 , H01G4/12 , H01G9/00
摘要： A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.
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7.发明申请MULTI-LEVEL THIN FILM CAPACITOR ON A CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US20140037835A1
公开(公告)日：2014-02-06
申请号：US14035195
申请日：2013-09-24
申请人： BlackBerry Limited
CPC分类号： H01G4/38 , H01G4/33 , H01G13/04 , H01L27/016 , H05K1/0306 , H05K1/162 , H05K3/38 , H05K3/388 , H05K2201/0175 , H05K2201/0179 , Y10T29/49126 , Y10T29/49155
摘要： In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
摘要翻译： 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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8.发明申请公开(公告)号：US20190259540A1
公开(公告)日：2019-08-22
申请号：US15901468
申请日：2018-02-21
申请人： BlackBerry Limited
IPC分类号： H01G7/06
摘要： A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.
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公开(公告)号：US10332687B2
公开(公告)日：2019-06-25
申请号：US15791176
申请日：2017-10-23
申请人： BlackBerry Limited
IPC分类号： H01G7/06 , H01G9/00 , H01L49/02 , H01L21/306
摘要： A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.
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公开(公告)号：US20190123131A1
公开(公告)日：2019-04-25
申请号：US15791177
申请日：2017-10-23
申请人： BlackBerry Limited
IPC分类号： H01L49/02 , H01G7/06 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/3213 , H01L21/283
摘要： A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
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