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公开(公告)号：US20230419010A1
公开(公告)日：2023-12-28
申请号：US18081522
申请日：2022-12-14
IPC分类号： G06F30/39 , H01L21/67 , H01L21/683 , H01L25/065 , H01L25/00
CPC分类号： G06F30/39 , H01L21/67144 , G06F2111/14 , H01L25/0657 , H01L25/50 , H01L21/6835
摘要： Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
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公开(公告)号：US20230118578A1
公开(公告)日：2023-04-20
申请号：US18081165
申请日：2022-12-14
IPC分类号： G06F30/39 , H01L21/67 , H01L21/683 , H01L25/065 , H01L25/00
摘要： Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
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公开(公告)号：US20210350061A1
公开(公告)日：2021-11-11
申请号：US17273713
申请日：2019-09-06
IPC分类号： G06F30/39 , H01L25/00 , H01L21/683 , H01L21/67 , H01L25/065
摘要： Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
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4.发明申请公开(公告)号：US20220270930A1
公开(公告)日：2022-08-25
申请号：US17735476
申请日：2022-05-03
发明人： Sidlgata V. Sreenivasan , Akhila Mallavarapu , Jaydeep Kulkarni , Michael Watts , Sanjay Banerjee
IPC分类号： H01L21/8234 , H01L29/786 , H01L29/66 , H01L27/088 , H01L27/11 , H01L21/3065 , H01L29/423 , H01L21/306
摘要： A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
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公开(公告)号：US20210366771A1
公开(公告)日：2021-11-25
申请号：US16957046
申请日：2018-12-21
发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal
IPC分类号： H01L21/768 , H01L23/48 , H01L23/538 , H01L23/544 , H01L27/06 , H01L25/00 , H01L25/065 , H01L23/00
摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
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公开(公告)号：US12094775B2
公开(公告)日：2024-09-17
申请号：US18081047
申请日：2022-12-14
发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/544 , H01L25/00 , H01L25/065 , H01L27/06
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5386 , H01L23/544 , H01L24/83 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/32145 , H01L2224/8013 , H01L2224/95001 , H01L2225/06544 , H01L2924/1437
摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
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7.发明授权公开(公告)号：US11355397B2
公开(公告)日：2022-06-07
申请号：US16872651
申请日：2020-05-12
发明人： Sidlgata V. Sreenivasan , Akhila Mallavarapu , Jaydeep Kulkarni , Michael Watts , Sanjay Banerjee
IPC分类号： H01L21/8234 , H01L29/786 , H01L29/66 , H01L27/088 , H01L27/11 , H01L21/3065 , H01L29/423 , H01L21/306
摘要： A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
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公开(公告)号：US12079557B2
公开(公告)日：2024-09-03
申请号：US17273713
申请日：2019-09-06
IPC分类号： G06F30/39 , H01L21/67 , H01L21/683 , H01L25/00 , H01L25/065 , G06F111/14 , G06F113/18
CPC分类号： G06F30/39 , H01L21/67144 , H01L21/6835 , H01L25/0657 , H01L25/50 , G06F2111/14 , G06F2113/18 , H01L2221/68327 , H01L2221/68363 , H01L2221/68381 , H01L2225/06544
摘要： Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
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公开(公告)号：US20230116581A1
公开(公告)日：2023-04-13
申请号：US18081047
申请日：2022-12-14
发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal
IPC分类号： H01L21/768 , H01L23/48 , H01L23/538 , H01L23/544 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06
摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
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10.发明授权公开(公告)号：US11881435B2
公开(公告)日：2024-01-23
申请号：US17735476
申请日：2022-05-03
发明人： Sidlgata V. Sreenivasan , Akhila Mallavarapu , Jaydeep Kulkarni , Michael Watts , Sanjay Banerjee
IPC分类号： H01L21/8234 , H01L29/786 , H01L29/66 , H01L27/088 , H01L21/3065 , H01L29/423 , H01L21/306 , H10B10/00
CPC分类号： H01L21/823431 , H01L21/3065 , H01L21/30604 , H01L27/0886 , H01L29/42392 , H01L29/66795 , H01L29/78696 , H10B10/12
摘要： A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
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