专利检索 ap:("Board of Regents, The University of Texas System") AND inv:"Ovadia Abed" 第 1 页

1.

发明授权
Roll-to-roll programmable film imprint lithography 有权

公开(公告)号：US11669009B2

公开(公告)日：2023-06-06

申请号：US16322842

申请日：2017-08-03

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Shrawan Singhal , Ovadia Abed , Lawrence Dunn , Paras Ajay , Ofodike Ezekoye

IPC分类号： G03F7/00 , B82Y40/00 , G01Q60/24

CPC分类号： G03F7/0002 , B82Y40/00 , G01Q60/24

摘要： A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

2.

发明授权
Fabricating large area multi-tier nanostructures 有权

公开(公告)号：US09972698B1

公开(公告)日：2018-05-15

申请号：US15904757

申请日：2018-02-26

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Praveen Joseph , Ovadia Abed , Michelle Grigas , Akhila Mallavarapu , Paras Ajay

IPC分类号： H01L29/66 , H01L21/311 , H01L21/308 , H01L21/306 , H01L21/762 , H01L21/285 , G02B6/124 , G03F7/00 , H01L21/033 , H01L21/027 , H01L21/02 , H01L49/02

CPC分类号： H01L29/6659 , G02B6/124 , G03F7/0002 , H01L21/02164 , H01L21/0228 , H01L21/0271 , H01L21/0337 , H01L21/2855 , H01L21/30604 , H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/76224 , H01L28/90 , H01L29/665 , H01L29/66515 , H01L29/6653 , H01L29/66545

摘要： Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

3.

发明授权
Nanoscale-aligned three-dimensional stacked integrated circuit 有权

公开(公告)号：US11600525B2

公开(公告)日：2023-03-07

申请号：US16957046

申请日：2018-12-21

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal

IPC分类号： H01L23/538 , H01L23/544 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06

摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

4.

发明申请
ROLL-TO-ROLL NANOIMPRINT LITHOGRAPHY TOOLS AND PROCESSES 有权

公开(公告)号：US20220229361A1

公开(公告)日：2022-07-21

申请号：US17611105

申请日：2020-05-13

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Parth Pandya , Shrawan Singhal , Paras Ajay , Ziam Ghaznavi , Ovadia Abed , Michael Watts

IPC分类号： G03F7/00

摘要： A method and system for configuring ultraviolet (UV)-based nanoimprint lithography (NIL) for roll-to-roll (R2R) processing, which combines the benefits of inexpensive R2R processing with the precise nanoscale patterning afforded by NIL. Furthermore, an R2R fabrication process is used to create nanoscale copper (Cu) metal mesh electrodes on flexible polycarbonate substrates and rigid quartz substrates employing jet-and-flash nanoimprint lithography (J-FIL), linear ion source etching (LIS) and selective electroless Cu metallization (ECu) using a palladium (Pd) seed layer.

5.

发明申请
PORTABLE SYSTEM FOR PROVIDING BROAD ACCESS TO MICRO- AND NANO-SCALE TECHNOLOGIES 审中-公开

公开(公告)号：US20190139456A1

公开(公告)日：2019-05-09

申请号：US16087193

申请日：2017-03-21

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Shrawan Singhal , Ovadia Abed , Lawrence Dunn , Aseem Sayal , Benjamin Eynon

IPC分类号： G09B25/02 , G09B7/00 , G09B19/00

摘要： A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently.

6.

发明授权
Nanoshape patterning techniques that allow high-speed and low-cost fabrication of nanoshape structures 有权

公开(公告)号：US10026609B2

公开(公告)日：2018-07-17

申请号：US14921866

申请日：2015-10-23

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Anshuman Cherala , Meghali Chopra , Roger Bonnecaze , Ovadia Abed , Bailey Yin , Akhila Mallavarapu , Shrawan Singhal , Brian Gawlik

IPC分类号： H01L21/02 , G03F7/00 , H01L21/308 , B81C1/00 , B82Y40/00 , G11B5/74 , H01L29/94

摘要： A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.

7.

发明公开
HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE 审中-公开

公开(公告)号：US20240332056A1

公开(公告)日：2024-10-03

申请号：US18739152

申请日：2024-06-10

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Mark McDermott , Shrawan Singhal , Ovadia Abed , Lawrence Dunn , Vipul Goyal , Michael Cullinan

IPC分类号： H01L21/683 , B81C99/00 , G06F30/392 , G06F30/396 , G06F30/398 , G06F117/10 , H01L23/544

CPC分类号： H01L21/6835 , B81C99/002 , G06F30/392 , G06F30/396 , G06F30/398 , H01L21/6838 , H01L23/544 , G06F2117/10 , H01L2221/68309 , H01L2221/68322 , H01L2221/68354 , H01L2221/68368 , H01L2221/68381 , H01L2223/54426 , H01L2223/54473

摘要： A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

8.

发明授权
Nanoscale-aligned three-dimensional stacked integrated circuit 有权

公开(公告)号：US12094775B2

公开(公告)日：2024-09-17

申请号：US18081047

申请日：2022-12-14

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal

IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/544 , H01L25/00 , H01L25/065 , H01L27/06

CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5386 , H01L23/544 , H01L24/83 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/32145 , H01L2224/8013 , H01L2224/95001 , H01L2225/06544 , H01L2924/1437

摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).