公开(公告)号：US20230285966A1

公开(公告)日：2023-09-14

申请号：US18018546

申请日：2021-07-29

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Aryan Mehboudi ,  Akhila Mallavarapu ,  Paras Ajay ,  Raul Marcel Lema Galindo ,  Mark Hrdy

IPC分类号： B01L3/00 ,  G01N21/65 ,  B01D67/00 ,  B01D69/02 ,  B01D71/02

CPC分类号： B01L3/502753 ,  G01N21/658 ,  B01D67/0062 ,  B01D69/02 ,  B01D71/0213 ,  B01D2325/08 ,  B01L2300/0636 ,  B01L2300/0681 ,  B01L2200/0652 ,  B01L2400/0487

摘要： A diagnostic chip for detecting biomarkers and trace amounts of nanoparticles in chemical mixtures or in water. The diagnostic chip includes one or more inputs, where a sample containing differently sized particles is introduced into at least one of these inputs. Furthermore, the diagnostic chip includes multiple separation regions, where the sample is pressurized as it passes through the separation regions. Each separation region includes a deterministic lateral displacement array, where the deterministic lateral displacement array in two or more of these separation regions has a different etch depth profile. In this manner, the diagnostic chip effectively detects biomarkers and trace amounts of nanoparticles in chemical mixtures or in water.

公开(公告)号：US20230124676A1

公开(公告)日：2023-04-20

申请号：US18081478

申请日：2022-12-14

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Mark McDermott ,  Jaydeep Kulkarni

IPC分类号： G06F30/39 ,  H01L21/67 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00

摘要： Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

公开(公告)号：US11600525B2

公开(公告)日：2023-03-07

申请号：US16957046

申请日：2018-12-21

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Ovadia Abed ,  Mark McDermott ,  Jaydeep Kulkarni ,  Shrawan Singhal

IPC分类号： H01L23/538 ,  H01L23/544 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06

摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

公开(公告)号：US20220229361A1

公开(公告)日：2022-07-21

申请号：US17611105

申请日：2020-05-13

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Parth Pandya ,  Shrawan Singhal ,  Paras Ajay ,  Ziam Ghaznavi ,  Ovadia Abed ,  Michael Watts

IPC分类号： G03F7/00

摘要： A method and system for configuring ultraviolet (UV)-based nanoimprint lithography (NIL) for roll-to-roll (R2R) processing, which combines the benefits of inexpensive R2R processing with the precise nanoscale patterning afforded by NIL. Furthermore, an R2R fabrication process is used to create nanoscale copper (Cu) metal mesh electrodes on flexible polycarbonate substrates and rigid quartz substrates employing jet-and-flash nanoimprint lithography (J-FIL), linear ion source etching (LIS) and selective electroless Cu metallization (ECu) using a palladium (Pd) seed layer.

公开(公告)号：US20160307790A1

公开(公告)日：2016-10-20

申请号：US15134179

申请日：2016-04-20

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Andrew Westfahl ,  Paras Ajay

IPC分类号： H01L21/687 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G03F7/707 ,  H01L21/6875

摘要： A pin mechanism and a method for reducing backside particle induced out-of-plane distortions in semiconductor wafers involving such pin mechanisms. Geometric parameters of the pin are optimized so as to maximize the height of a particle trapped between a backside of the wafer and one of the contact lands without exceeding a selected maximum out-of-plane distortion. These geometric parameters are optimized in various designs of the pin mechanism, such as a pin mechanism that includes secondary leaf-type flexures attached to the contact lands and a single stem attached to a base portion of a cross-member of the pin. An alternative pin mechanism includes notch-type flexures, as opposed to secondary leaf-type flexures, connected to the cross-member of the pin. Furthermore, a plurality of stems are attached to the base portion of the cross-member of the pin. Alternatively, such a pin mechanism may utilize a different number of stems (e.g., one stem).

摘要翻译： 引脚机构和减少背面微粒引起的半导体晶片的平面外失真的方法，涉及这种引脚机构。 引脚的几何参数被优化，以便最大化在晶片的背面和接触焊盘之一之间捕获的颗粒的高度，而不超过选定的最大的平面外失真。 这些几何参数在销机构的各种设计中得到优化，例如包括附接到接触平台的次级叶片式弯曲件的销机构和附接到销的横向构件的基部的单个杆。 替代的销钉机构包括与第二叶片类型的弯曲件相对应的凹口型挠曲件，其连接到销的横向构件。 此外，多个杆连接到销的横梁的基部。 或者，这种针机构可以利用不同数量的杆（例如，一个杆）。

公开(公告)号：US20230163013A1

公开(公告)日：2023-05-25

申请号：US18090471

申请日：2022-12-28

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Akhila Mallavarapu ,  Crystal Barrera

IPC分类号： H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687 ,  H01L23/544 ,  H01L27/06

CPC分类号： H01L21/6833 ,  H01L21/3065 ,  H01L21/6838 ,  H01L21/67069 ,  H01L21/68721 ,  H01L21/67259 ,  H01L21/6836 ,  H01L23/544 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2223/54426

摘要： A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

公开(公告)号：US11469131B2

公开(公告)日：2022-10-11

申请号：US16472766

申请日：2017-12-22

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Mark McDermott ,  Shrawan Singhal ,  Ovadia Abed ,  Lawrence Dunn ,  Vipul Goyal ,  Michael Cullinan

IPC分类号： H01L21/683 ,  G06F30/392 ,  G06F30/398 ,  G06F30/396 ,  B81C99/00 ,  H01L23/544 ,  G06F117/10

摘要： A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

公开(公告)号：US20210366771A1

公开(公告)日：2021-11-25

申请号：US16957046

申请日：2018-12-21

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Ovadia Abed ,  Mark McDermott ,  Jaydeep Kulkarni ,  Shrawan Singhal

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/544 ,  H01L27/06 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

摘要： A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

公开(公告)号：US20210134640A1

公开(公告)日：2021-05-06

申请号：US16472766

申请日：2017-12-22

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Mark McDermott ,  Shrawan Singhal ,  Ovadia Abed ,  Lawrence Dunn ,  Vipul Goyal ,  Michael Cullinan

IPC分类号： H01L21/683 ,  B81C99/00 ,  G06F30/398 ,  G06F30/396 ,  G06F30/392 ,  H01L23/544

摘要： A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

公开(公告)号：US09941389B2

公开(公告)日：2018-04-10

申请号：US15133007

申请日：2016-04-19

申请人： Board of Regents, The University of Texas System

发明人： Sidlgata V. Sreenivasan ,  Praveen Joseph ,  Ovadia Abed ,  Michelle Grigas ,  Akhila Mallavarapu ,  Paras Ajay

IPC分类号： H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  G03F7/00 ,  G02B6/124 ,  H01L21/02 ,  H01L49/02

CPC分类号： H01L29/6659 ,  G02B6/124 ,  G03F7/0002 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L28/90 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545

摘要： Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.