Non-volatile memory devices
    1.
    发明授权
    Non-volatile memory devices 失效
    非易失性存储器件

    公开(公告)号:US07332768B2

    公开(公告)日:2008-02-19

    申请号:US11367288

    申请日:2006-03-02

    IPC分类号: H01L29/788

    摘要: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.

    摘要翻译: 公开了非易失性存储器件。 在第一示例性非易失性存储器件中,通过相同的绝缘屏障执行存储器件的编程和擦除,而不使用复杂的对称结构。 在示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外,在示例性装置中,通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中,包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现,或者可以在其他存储器件中实现。 在第二示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中,隧道式负电荷载体被存储在离散存储位置。

    Method for improving erase saturation in non-volatile memory devices and devices obtained thereof
    2.
    发明申请
    Method for improving erase saturation in non-volatile memory devices and devices obtained thereof 有权
    用于改善非易失性存储器件及其获得的器件中的擦除饱和度的方法

    公开(公告)号:US20080185632A1

    公开(公告)日:2008-08-07

    申请号:US11976976

    申请日:2007-10-29

    IPC分类号: H01L29/788 H01L29/792

    摘要: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.

    摘要翻译: 公开了非易失性存储器件。 在第一示例性非易失性存储器件中,通过相同的绝缘屏障执行存储器件的编程和擦除,而不使用复杂的对称结构。 在示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外,在示例性装置中,通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中,包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现,或者可以在其他存储器件中实现。 在第二示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中,隧道式负电荷载体被存储在离散存储位置。

    Insulating barrier, NVM bandgap design
    3.
    发明授权
    Insulating barrier, NVM bandgap design 有权
    绝缘屏障,NVM带隙设计

    公开(公告)号:US06784484B2

    公开(公告)日:2004-08-31

    申请号:US10131923

    申请日:2002-04-25

    IPC分类号: H01L29788

    摘要: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

    摘要翻译: 公开了在第一导电区域和第二导电区域之间延伸的绝缘屏障。 提供绝缘屏障用于将电荷载体从第一区域延伸到第二区域,绝缘屏障包括接触第一区域的第一部分和接触第一部分并朝第二区域延伸的第二部分,第一部分基本上比 第二部分,第一部分构造在第一电介质中,第二部分构造在不同于第一电介质的第二电介质中,第一电介质具有比第二电介质低的介电常数。

    Insulating barrier, NVM bandgap design
    5.
    发明申请
    Insulating barrier, NVM bandgap design 有权
    绝缘屏障,NVM带隙设计

    公开(公告)号:US20050017288A1

    公开(公告)日:2005-01-27

    申请号:US10880415

    申请日:2004-06-28

    摘要: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.

    摘要翻译: 公开了在第一导电区域和第二导电区域之间延伸的绝缘屏障。 提供绝缘屏障用于将电荷载体从第一区域延伸到第二区域,绝缘屏障包括接触第一区域的第一部分和接触第一部分并朝第二区域延伸的第二部分,第一部分基本上比 第二部分,第一部分构造在第一电介质中,第二部分构造在不同于第一电介质的第二电介质中,第一电介质具有比第二电介质低的介电常数。

    Non-volatile memory devices
    6.
    发明申请
    Non-volatile memory devices 失效
    非易失性存储器件

    公开(公告)号:US20060175656A1

    公开(公告)日:2006-08-10

    申请号:US11367288

    申请日:2006-03-02

    IPC分类号: H01L29/788 H01L21/8238

    摘要: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.

    摘要翻译: 公开了非易失性存储器件。 在第一示例性非易失性存储器件中,通过相同的绝缘屏障执行存储器件的编程和擦除,而不使用复杂的对称结构。 在示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外,在示例性装置中,通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中,包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现,或者可以在其他存储器件中实现。 在第二示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中,隧道式负电荷载体被存储在离散存储位置。

    Scalable interpoly dielectric stacks with improved immunity to program saturation
    7.
    发明授权
    Scalable interpoly dielectric stacks with improved immunity to program saturation 有权
    可扩展的互补电介质堆叠,具有提高的编程饱和度的免疫力

    公开(公告)号:US08441064B2

    公开(公告)日:2013-05-14

    申请号:US13207961

    申请日:2011-08-11

    IPC分类号: H01L29/72

    摘要: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

    摘要翻译: 描述了用于制造非易失性存储器件的方法。 该方法包括在氧化硅消耗材料中生长一层,例如。 DyScO,在存储电荷的层的上层之上。 还描述了非易失性存储器件。 在非易失性存储器件中,多晶硅/绝缘电介质包括一层二氧化硅消耗材料, DyScO,在存储电荷的层的上层的顶部,消耗了上层的至少一部分的氧化硅消耗材料。

    Method for improving erase saturation in non-volatile memory devices and devices obtained thereof
    8.
    发明授权
    Method for improving erase saturation in non-volatile memory devices and devices obtained thereof 有权
    用于改善非易失性存储器件及其获得的器件中的擦除饱和度的方法

    公开(公告)号:US07626226B2

    公开(公告)日:2009-12-01

    申请号:US11976976

    申请日:2007-10-29

    申请人: Bogdan Govoreanu

    发明人: Bogdan Govoreanu

    IPC分类号: H01L29/94

    摘要: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.

    摘要翻译: 公开了非易失性存储器件。 在第一示例性非易失性存储器件中,通过相同的绝缘屏障执行存储器件的编程和擦除,而不使用复杂的对称结构。 在示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外,在示例性装置中,通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中,包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现,或者可以在其他存储器件中实现。 在第二示例性装置中,通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中,隧道式负电荷载体被存储在离散存储位置。

    Scalable Interpoly Dielectric Stacks With Improved Immunity To Program Saturation
    9.
    发明申请
    Scalable Interpoly Dielectric Stacks With Improved Immunity To Program Saturation 有权
    可扩展的Interpoly电介质堆叠,具有提高程序饱和度的抗扰度

    公开(公告)号:US20090166715A1

    公开(公告)日:2009-07-02

    申请号:US12338015

    申请日:2008-12-18

    IPC分类号: H01L29/792 H01L21/28

    摘要: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

    摘要翻译: 描述了用于制造非易失性存储器件的方法。 该方法包括在氧化硅消耗材料中生长一层,例如。 DyScO,在存储电荷的层的上层之上。 还描述了非易失性存储器件。 在非易失性存储器件中,多晶硅/绝缘电介质包括一层二氧化硅消耗材料, DyScO,在存储电荷的层的上层的顶部,消耗了上层的至少一部分的氧化硅消耗材料。

    Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same
    10.
    发明授权
    Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same 有权
    具有提高抗擦除饱和度的非易失性存储器件及其制造方法

    公开(公告)号:US08119511B2

    公开(公告)日:2012-02-21

    申请号:US13080562

    申请日:2011-04-05

    IPC分类号: H01L21/28

    摘要: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

    摘要翻译: 一种非易失性存储器件,其具有位于第二电介质(互补或阻塞电介质)顶部的控制栅极,至少与第二电介质接触的控制栅极的底层被构造成具有预定义的高功函数的材料 并且在完全器件制造之后显示出与一组高k材料接触时降低其功能的趋势。 至少第二电介质的顶层将控制栅极的底层与第二电介质的其余部分分开,以预定的高k材料构成,选择在组外部,以避免工作功能的降低 控制门底层的材料。 在制造方法中,在施加控制栅极之前,在第二电介质中产生顶层。