公开(公告)号：US07964039B2

公开(公告)日：2011-06-21

申请号：US12205596

申请日：2008-09-05

Applicant: Adam Michal Urbanowicz ,  Mikhaïl Baklanov ,  Denis Shamiryan ,  Stefan De Gendt

Inventor： Adam Michal Urbanowicz ,  Mikhaïl Baklanov ,  Denis Shamiryan ,  Stefan De Gendt

IPC: B08B7/00 ,  B08B7/04 ,  B08B9/00

CPC classification number: C23C16/4405 ,  B08B7/0057

Abstract: An improved reaction chamber cleaning process is provided for removing water residues that makes use of noble-gas plasma reactions. The method is easy applicable and may be combined with standard cleaning procedure. A noble-gas plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules to form electronically excited oxygen atoms is used to remove the adsorbed water.

Abstract translation: 提供了一种改进的反应室清洁方法，用于除去利用惰性气体等离子体反应的水残余物。 该方法易于应用，可与标准清洗程序结合使用。 使用能够破坏水分子形成电子激发的氧原子的高能量EUV光子（E> 20eV）的稀有气体等离子体（例如He）去除吸附的水。

公开(公告)号：US08211812B2

公开(公告)日：2012-07-03

申请号：US12104353

申请日：2008-04-16

Applicant: Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

Inventor： Lars-Ake Ragnarsson ,  Paul Zimmerman ,  Kazuhiko Yamamoto ,  Tom Schram ,  Wim Deweerd ,  David Brunco ,  Stefan De Gendt ,  Wilfried Vandervorst

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/316 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract translation: 本发明的一个方面涉及一种用于制造高k电介质层的方法。 该方法包括在基底上沉积具有第一厚度的高k电介质材料的层。 高k电介质材料具有体积密度值，第一厚度使得高k电介质层具有至少高k电介质材料的体积密度值减去约10％的密度。 该方法还包括将高k电介质层变薄至第二厚度。 另一个发明方面涉及包括通过该方法制造的高k电介质层的半导体器件。

公开(公告)号：US08021948B2

公开(公告)日：2011-09-20

申请号：US12338015

申请日：2008-12-18

Applicant: Bogdan Govoreanu ,  Stefan De Gendt ,  Sven Van Elshocht ,  Tom Schram

Inventor： Bogdan Govoreanu ,  Stefan De Gendt ,  Sven Van Elshocht ,  Tom Schram

IPC: H01L29/72

CPC classification number: H01L29/7881 ,  H01L29/513 ,  H01L29/66825

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract translation: 描述了用于制造非易失性存储器件的方法。 该方法包括在氧化硅消耗材料中生长一层，例如。 DyScO，在存储电荷的层的上层之上。 还描述了非易失性存储器件。 在非易失性存储器件中，多晶硅/绝缘电介质包括一层二氧化硅消耗材料， DyScO，在存储电荷的层的上层的顶部，消耗了上层的至少一部分的氧化硅消耗材料。

公开(公告)号：US09024299B2

公开(公告)日：2015-05-05

申请号：US12578439

申请日：2009-10-13

Applicant: Zilan Li ,  Joshua Tseng ,  Thomas Witters ,  Stefan De Gendt

Inventor： Zilan Li ,  Joshua Tseng ,  Thomas Witters ,  Stefan De Gendt

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/823842 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material.

Abstract translation: 公开了一种制造双功能半导体器件的方法及其制造的器件。 一方面，一种方法包括在半导体衬底上提供栅介质层。 该方法还包括在栅介电层上形成金属层。 该方法还包括在金属层上形成栅极填充材料层。 该方法还包括图案化栅极介电层，金属层和栅极填充层以形成第一和第二栅极叠层。 该方法还包括仅从第二栅极堆叠去除栅极填充材料，从而暴露下面的金属层。 该方法还包括将暴露的金属层转变成金属氧化物层。 该方法还包括用另一种栅极填充材料重新构造第二栅极堆叠。

公开(公告)号：US20110291179A1

公开(公告)日：2011-12-01

申请号：US13207961

申请日：2011-08-11

Applicant: Bogdan Govoreanu ,  Stefan De Gendt ,  Sven Van Elshocht ,  Tom Schram

Inventor： Bogdan Govoreanu ,  Stefan De Gendt ,  Sven Van Elshocht ,  Tom Schram

IPC: H01L29/792

CPC classification number: H01L29/7881 ,  H01L29/513 ,  H01L29/66825

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract translation: 描述了用于制造非易失性存储器件的方法。 该方法包括在氧化硅消耗材料中生长一层，例如。 DyScO，在存储电荷的层的上层之上。 还描述了非易失性存储器件。 在非易失性存储器件中，多晶硅/绝缘电介质包括一层二氧化硅消耗材料， DyScO，在存储电荷的层的上层的顶部，消耗了上层的至少一部分的氧化硅消耗材料。

公开(公告)号：US20090050982A1

公开(公告)日：2009-02-26

申请号：US11754820

申请日：2007-05-29

Applicant: Luigi Pantisano ,  Tom Schram ,  Stefan De Gendt ,  Amal Akheyar ,  XinPeng Wang ,  Mingfu Li ,  HongYu Yu

Inventor： Luigi Pantisano ,  Tom Schram ,  Stefan De Gendt ,  Amal Akheyar ,  XinPeng Wang ,  Mingfu Li ,  HongYu Yu

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/785

Abstract: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The interfacial layer comprises a lanthanum hafnium oxide material for modulating the effective work function of the metal gate. The gate dielectric material in contact with the interfacial layer is different that the interfacial layer material. A method for its manufacture is also provided and its applications.

Abstract translation: 描述了一种新的MOSFET器件，其包括金属栅极电极，栅极电介质和界面层。 界面层包括用于调节金属栅极的有效功函数的镧氧化镧材料。 与界面层接触的栅极电介质材料与界面层材料不同。 还提供了其制造方法及其应用。

公开(公告)号：US20080254605A1

公开(公告)日：2008-10-16

申请号：US11735926

申请日：2007-04-16

Applicant: David Brunco ,  Lars-Ake Ragnarsson ,  Stefan De Gendt ,  Zsolt Tokei

Inventor： David Brunco ,  Lars-Ake Ragnarsson ,  Stefan De Gendt ,  Zsolt Tokei

IPC: H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L29/517

Abstract: One inventive aspect is related to a method of minimizing the final thickness of an interfacial oxide layer between a semiconductor material and a high dielectric constant material. The method comprises depositing a covering layer on the high dielectric constant material. The method further comprises removing adsorbed/absorbed water from the high dielectric constant material prior to depositing the covering layer. The removal of adsorbed/absorbed water is preferably done by a degas treatment. The covering layer may be a gate electrode or a spacer dielectric.

Abstract translation: 一个发明方面涉及使半导体材料和高介电常数材料之间的界面氧化物层的最终厚度最小化的方法。 该方法包括在高介电常数材料上沉积覆盖层。 该方法还包括在沉积覆盖层之前从高介电常数材料中除去吸附/吸收的水。 吸附/吸收的水的去除优选通过脱气处理进行。 覆盖层可以是栅电极或间隔电介质。

公开(公告)号：US20070272967A1

公开(公告)日：2007-11-29

申请号：US11754775

申请日：2007-05-29

Applicant: Luigi Pantisano ,  Tom Schram ,  Stefan De Gendt ,  Amal Akheyar ,  Geoffrey Pourtois ,  HongYu Yu

Inventor： Luigi Pantisano ,  Tom Schram ,  Stefan De Gendt ,  Amal Akheyar ,  Geoffrey Pourtois ,  HongYu Yu

IPC: H01L29/788 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/785

Abstract: A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The electrostatic potential at an interface between the gate electrode and the gate dielectric of a MOSFET device can be controlled by introducing one or more interfacial layer(s) of a dielectric material, at the monolayer(s) level (i.e., preferably two monolayers), between the gate electrode and the gate dielectric. A method for its manufacture is also provided and its applications.

Abstract translation: 描述了一种新的MOSFET器件，其包括金属栅极电极，栅极电介质和界面层。 可以通过在单层（即，优选两个单层）处引入介电材料的一个或多个界面层来控制MOSFET器件的栅极电极和栅极电介质之间的界面处的静电电位， ，在栅极电极和栅极电介质之间。 还提供了其制造方法及其应用。

公开(公告)号：US20110253981A1

公开(公告)日：2011-10-20

申请号：US13083387

申请日：2011-04-08

Applicant: Rita Rooyackers ,  Daniele Leonelli ,  Anne Vandooren ,  Anne S. Verhulst ,  Roger Loo ,  Stefan De Gendt

Inventor： Rita Rooyackers ,  Daniele Leonelli ,  Anne Vandooren ,  Anne S. Verhulst ,  Roger Loo ,  Stefan De Gendt

IPC: H01L27/092 ,  H01L21/8238 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L21/823885 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66356

Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Abstract translation: 本公开提供了一种用于制造至少一个纳米线隧道场效应晶体管（TFET）半导体器件的方法。 该方法包括提供包括沟道材料层的堆叠，其顶部具有牺牲材料层，从堆叠中去除材料，以便从沟道材料层和牺牲材料层形成至少一个纳米线，并且代替 通过异质结材料在至少一个纳米线中的牺牲材料。 根据本公开的实施例的方法是有利的，因为其能够容易地制造互补的TFET。

公开(公告)号：US20110006406A1

公开(公告)日：2011-01-13

申请号：US12831935

申请日：2010-07-07

Applicant: Adam Michal Urbanowicz ,  Patrick Verdonck ,  Denis Shamiryan ,  Kris Vanstreels ,  Mikhail Baklanov ,  Stefan De Gendt

Inventor： Adam Michal Urbanowicz ,  Patrick Verdonck ,  Denis Shamiryan ,  Kris Vanstreels ,  Mikhail Baklanov ,  Stefan De Gendt

IPC: H01L29/06 ,  H01L21/31

CPC classification number: C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/7682 ,  H01L2221/1047

Abstract: A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step.

Abstract translation: 提供一种制备孔隙率高于50％和高于5GPa的高弹性模量的无致孔剂残留超低k膜的方法。 该方法开始于使用等离子体增强化学气相沉积（PE-CVD）或化学气相沉积（CVD）将SiCOH膜沉积到衬底上，然后首先在升高的晶片温度下在200℃范围内进行原子氢处理 至350℃以除去所有的致孔剂，然后进行UV辅助热固化步骤。