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公开(公告)号：US07332768B2
公开(公告)日：2008-02-19
申请号：US11367288
申请日：2006-03-02
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885 , H01L29/792
摘要： Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.
摘要翻译： 公开了非易失性存储器件。 在第一示例性非易失性存储器件中，通过相同的绝缘屏障执行存储器件的编程和擦除，而不使用复杂的对称结构。 在示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外，在示例性装置中，通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中，包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现，或者可以在其他存储器件中实现。 在第二示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中，隧道式负电荷载体被存储在离散存储位置。
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公开(公告)号：US20060175656A1
公开(公告)日：2006-08-10
申请号：US11367288
申请日：2006-03-02
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885 , H01L29/792
摘要： Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.
摘要翻译： 公开了非易失性存储器件。 在第一示例性非易失性存储器件中，通过相同的绝缘屏障执行存储器件的编程和擦除，而不使用复杂的对称结构。 在示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外，在示例性装置中，通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中，包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现，或者可以在其他存储器件中实现。 在第二示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中，隧道式负电荷载体被存储在离散存储位置。
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3.发明申请Method for improving erase saturation in non-volatile memory devices and devices obtained thereof 有权用于改善非易失性存储器件及其获得的器件中的擦除饱和度的方法公开(公告)号：US20080185632A1
公开(公告)日：2008-08-07
申请号：US11976976
申请日：2007-10-29
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885 , H01L29/792
摘要： Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.
摘要翻译： 公开了非易失性存储器件。 在第一示例性非易失性存储器件中，通过相同的绝缘屏障执行存储器件的编程和擦除，而不使用复杂的对称结构。 在示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 此外，在示例性装置中，通过将正载流子从电荷供应区域隧穿到电荷存储区域来实现擦除。 在第二示例性非易失性存储器件中，包括具有空间分布电荷存储区域的电荷存储区域。 这样的电荷存储区域可以在第一示例存储器件中实现，或者可以在其他存储器件中实现。 在第二示例性装置中，通过将负电荷载体从电荷供应区域隧穿到电荷存储区域来实现编程。 在第二示例性装置中，隧道式负电荷载体被存储在离散存储位置。
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公开(公告)号：US06784484B2
公开(公告)日：2004-08-31
申请号：US10131923
申请日：2002-04-25
IPC分类号： H01L29788
CPC分类号： H01L29/513 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885
摘要： An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
摘要翻译： 公开了在第一导电区域和第二导电区域之间延伸的绝缘屏障。 提供绝缘屏障用于将电荷载体从第一区域延伸到第二区域，绝缘屏障包括接触第一区域的第一部分和接触第一部分并朝第二区域延伸的第二部分，第一部分基本上比 第二部分，第一部分构造在第一电介质中，第二部分构造在不同于第一电介质的第二电介质中，第一电介质具有比第二电介质低的介电常数。
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公开(公告)号：US07026686B2
公开(公告)日：2006-04-11
申请号：US10880415
申请日：2004-06-28
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885
摘要： An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
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公开(公告)号：US20050017288A1
公开(公告)日：2005-01-27
申请号：US10880415
申请日：2004-06-28
IPC分类号： H01L21/28 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L29/513 , B82Y10/00 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7885
摘要： An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
摘要翻译： 公开了在第一导电区域和第二导电区域之间延伸的绝缘屏障。 提供绝缘屏障用于将电荷载体从第一区域延伸到第二区域，绝缘屏障包括接触第一区域的第一部分和接触第一部分并朝第二区域延伸的第二部分，第一部分基本上比 第二部分，第一部分构造在第一电介质中，第二部分构造在不同于第一电介质的第二电介质中，第一电介质具有比第二电介质低的介电常数。
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公开(公告)号：US08263459B2
公开(公告)日：2012-09-11
申请号：US12836545
申请日：2010-07-14
申请人： Pieter Blomme
发明人： Pieter Blomme
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521
摘要： Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures.
摘要翻译： 一种用于制造非易失性存储器的方法，所述非易失性存储器包括半导体材料的衬底上的至少一个存储单元阵列，所述存储器单元通过STI结构自对准并且彼此分离，所述存储单元包括具有 沿着存储器单元阵列的横截面中的倒T形，其中通过氧化浮置栅极的侧壁的上部部分形成反向T形，从而形成牺牲氧化物，随后在进一步蚀刻回时同时去除牺牲氧化物 STI结构。
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8.发明授权公开(公告)号：US08652902B2
公开(公告)日：2014-02-18
申请号：US13410843
申请日：2012-03-02
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825
摘要： Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
摘要翻译： 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。
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公开(公告)号：US20130341701A1
公开(公告)日：2013-12-26
申请号：US13877616
申请日：2011-10-06
申请人： Pieter Blomme , Gouri Sankar Kar
发明人： Pieter Blomme , Gouri Sankar Kar
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L21/764 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Disclosed are vertical semiconductor devices and methods of manufacturing vertical semiconductor devices. An example method includes providing a semiconductor substrate, and forming a stack of horizontal layers on the semiconductor substrate, where the horizontal layers are substantially parallel to a surface of the semiconductor substrate, and the horizontal layers comprise alternating conductive layers and dielectric layers. The method further includes forming a vertical channel region through the stack of horizontal layers, where the vertical channel region is substantially perpendicular to a surface of the semiconductor substrate, and the vertical channel region comprises sidewall surfaces. The method further includes forming a charge storage layer on regions of the sidewall surfaces of the vertical channel region that are in direct contact with conductive layers in the stack of horizontal layers and, at a distance from the vertical channel region, forming a vertical dielectric region through the stack of horizontal layers.
摘要翻译： 公开了垂直半导体器件和制造垂直半导体器件的方法。 示例性方法包括提供半导体衬底，并且在半导体衬底上形成水平层堆叠，其中水平层基本上平行于半导体衬底的表面，并且水平层包括交替的导电层和电介质层。 该方法还包括通过水平层的堆叠形成垂直沟道区域，其中垂直沟道区域基本上垂直于半导体衬底的表面，并且垂直沟道区域包括侧壁表面。 该方法还包括在垂直沟道区域的侧壁表面的与水平层堆叠中的导电层直接接触的区域上形成电荷存储层，并且在与垂直沟道区一定距离处形成垂直电介质区域 通过堆叠的水平层。
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10.发明申请公开(公告)号：US20120223378A1
公开(公告)日：2012-09-06
申请号：US13410843
申请日：2012-03-02
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825
摘要： Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
摘要翻译： 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。
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