公开(公告)号：US07312625B1

公开(公告)日：2007-12-25

申请号：US11449197

申请日：2006-06-08

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang ,  Jan L. de Jong

IPC: G01R31/00

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2858

Abstract: A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Abstract translation: 描述了用于制造用于超大规模集成（“VLSI”）处理的晶体管的测试电路及其使用方法。 晶体管形成阵列。 第一解码器耦合到晶体管的栅极并被配置为选择性地将电压传递到栅极。 第二解码器耦合到晶体管的漏极区域并且被配置为选择性地将电压传递到晶体管的漏极区域。 第三解码器耦合到晶体管的源极区域并且被配置为选择性地将电压传递到晶体管的源极区域。 第四解码器耦合到晶体管的体区，并且被配置为选择性地将电压传递到晶体管的体区。

公开(公告)号：US07688639B1

公开(公告)日：2010-03-30

申请号：US11974361

申请日：2007-10-12

Applicant: Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

Inventor： Sunhom Paak ,  Boon Yong Ang ,  Hsung Jai Im ,  Daniel Gitlin

IPC: G11C16/06

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/66833

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract translation: 使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。 第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。 在多晶硅栅极上生长热氧化物以提供隔离层。 氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

公开(公告)号：US20090224323A1

公开(公告)日：2009-09-10

申请号：US12043914

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract translation: MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。 然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。 测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。 测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。 将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

公开(公告)号：US08564023B2

公开(公告)日：2013-10-22

申请号：US12043914

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/52

CPC classification number: H01L27/101 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract translation: MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。 然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。 测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。 测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。 将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

公开(公告)号：US07834659B1

公开(公告)日：2010-11-16

申请号：US12043103

申请日：2008-03-05

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H03K19/173

CPC classification number: G11C17/18

Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.

Abstract translation: 通过对多个E保险丝应用第一编程脉冲将多个E保险丝编程到第一状态来编程E熔丝存储器阵列中的电子熔丝; 然后将第二编程脉冲施加到所述多个E熔丝中的至少一个选定的E熔丝，以将所选择的E熔丝编程到第二状态。

公开(公告)号：US07567449B2

公开(公告)日：2009-07-28

申请号：US11588775

申请日：2006-10-27

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

IPC: G11C17/00

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract translation: 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

公开(公告)号：US07923811B1

公开(公告)日：2011-04-12

申请号：US12043910

申请日：2008-03-06

Applicant: Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

Inventor： Hsung Jai Im ,  Sunhom Paak ,  Boon Yong Ang

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.

Abstract translation: 电子熔丝（“E-fuse”）单元形成在半导体衬底上。 电子熔断器单元具有熔丝元件，熔丝链从第一熔丝端子穿过厚电介质结构延伸到第二熔丝端子。 第一和第二熔丝端子通过薄的电介质层与半导体衬底分离。

公开(公告)号：US20080101146A1

公开(公告)日：2008-05-01

申请号：US11588775

申请日：2006-10-27

Applicant: Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

Inventor： Sunhom Paak ,  Hsung Jai Im ,  Boon Yong Ang

IPC: G11C17/18

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract translation: 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

公开(公告)号：US06627484B1

公开(公告)日：2003-09-30

申请号：US10274241

申请日：2002-10-18

Applicant: Boon Yong Ang

Inventor： Boon Yong Ang

IPC: H01L2176

CPC classification number: H01L21/76895 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches. Next, all of the exposed surfaces of the trenches are oxidized and the oxide at the trench bottom is removed to expose the underlying semiconductor material. The underlying semiconductor material is then silicided to form a buried interconnect. The wafer, including the trenches, is subsequently covered with oxide and chemical-mechanical polishing is used to remove excess oxide outside the trenches.

Abstract translation: 在与半导体器件一起使用的电路制造工艺流程的早期阶段期间，可以将掩埋互连件并入到绝缘体上的半导体晶片上。 掩埋互连提供了附加的互连层，从而可以实现互连所占用的硅片的整体降低。 埋置互连具有低电阻，并且可以通过使用硅化物来防止形成不期望的PN结。 掩埋互连及其制造方法包括：通过氧化在氧化层顶部形成有氧化层的S0I晶片，随后在氧化物层上形成氮化物层，然后选择性地蚀刻以形成两个沟槽， 不同的深度。 蚀刻沟槽的一些区域以去除沟槽中的所有半导体层以露出掩埋氧化物层。 在其他区域，半导体薄层留在沟槽的底部。 接下来，沟槽的所有暴露表面被氧化，并且去除沟槽底部的氧化物以露出下面的半导体材料。 然后将底层半导体材料硅化以形成掩埋互连。 包括沟槽的晶片随后被氧化物覆盖，并且使用化学机械抛光来除去沟槽外的过量氧化物。

公开(公告)号：US06328641B1

公开(公告)日：2001-12-11

申请号：US09496218

申请日：2000-02-01

Applicant: Boon Yong Ang ,  Kenneth R. Harris

Inventor： Boon Yong Ang ,  Kenneth R. Harris

IPC: B24B700

CPC classification number: B24B37/11 ,  B24B9/065 ,  B24B37/013 ,  B24B49/12

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad. The polishing surface of the polishing pad may be tapered such that the edge of an upper layer of material that is disposed further from the semiconductor wafer is disposed more inward toward the center of the semiconductor wafer such that the upper layer of material is not likely to delaminate and peel-off away from a lower abutting layer of material on the semiconductor wafer. Furthermore, a photodetector may determine sufficient polishing of the outer edge ring of the semiconductor wafer.

Abstract translation: 抛光半导体晶片的外边缘环，以防止在集成电路的制造期间沉积在半导体晶片的外边缘附近的至少一层材料的分层和剥离。 将半导体晶片安装在晶片卡盘上，并且保持半导体晶片的晶片卡盘旋转，使得半导体晶片旋转。 当半导体晶片旋转时，抛光垫朝向半导体晶片移动。 当抛光垫向半导体晶片移动以抛光半导体晶片的外边缘环时，抛光垫具有面向并接触半导体晶片的外边缘环的抛光表面。 外边缘环具有由抛光垫的抛光表面抛光的至少一层材料。 抛光垫的抛光表面可以是锥形的，使得更远离半导体晶片的材料的上层的边缘更靠近半导体晶片的中心设置，使得上层材料不可能 从半导体晶片上的下部邻接材料层剥离和剥离。 此外，光电检测器可以确定半导体晶片的外边缘环的充分抛光。