公开(公告)号：US07159048B2

公开(公告)日：2007-01-02

申请号：US10179816

申请日：2002-06-24

申请人： Bradley Roach ,  David Duckman ,  Eric Peel ,  Qing Xue

发明人： Bradley Roach ,  David Duckman ,  Eric Peel ,  Qing Xue

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

摘要翻译： DMA（直接存储器访问）交换块（DXB）处理器可以包括用于通过总线将数据从本地存储器写入主机存储器的接收处理器，例如外围部件互连扩展（PCI / X）总线和传输 处理器，用于将通过总线从主机存储器检索的数据写入本地存储器。 每个处理器可以包括高优先级队列和正常优先级队列。 控制程序生成DXB，每个DXB包括由控制程序分配的标签和对应于直接存储器访问操作的存储器描述符。 存储器描述符可以包括主机存储器描述符（地址/长度）和一个或多个本地存储器描述符。 控制程序将DXB写入高速缓存行溢出操作中的一个队列。 传送处理器可以包括两个通道寄存器，使处理器能够同时执行两个PCI / X数据传输。

公开(公告)号：US20070013705A1

公开(公告)日：2007-01-18

申请号：US11179221

申请日：2005-07-11

申请人： Bradley Roach ,  Raul Oteyza ,  David Duckman

发明人： Bradley Roach ,  Raul Oteyza ,  David Duckman

IPC分类号： G06F12/02

CPC分类号： G06F12/0223

摘要： Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

摘要翻译： 公开了当帧大小不是两倍的字节数时，将数据帧存储在帧缓冲器中，其大小适合于帧大小。 缓冲区大小选择为小于帧大小的最大二次幂。 当要存储数据帧时，可以将缓冲器数量乘以缓冲器大小以获得部分帧缓冲器地址Q.从帧大小中减去的缓冲器大小被称为剩余缓冲器大小， 并且缓冲器数量被有效地乘以残余缓冲器大小以获得残余帧缓冲器地址R.全帧缓冲器起始地址S = Q + R。 对于帧大小和缓冲器大小之间的差异是二分之一值的实现，可以使用二进制移位和相加来代替乘法器。

公开(公告)号：US06304910B1

公开(公告)日：2001-10-16

申请号：US08937065

申请日：1997-09-24

申请人： Bradley Roach ,  Peter Fiacco ,  Greg Scherer ,  Stuart Berman ,  David Duckman

发明人： Bradley Roach ,  Peter Fiacco ,  Greg Scherer ,  Stuart Berman ,  David Duckman

IPC分类号： G06F1300

CPC分类号： H04L49/9089 ,  H04L29/06 ,  H04L47/10 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9052 ,  H04L49/9094 ,  H04L69/12

摘要： A communication processor sends and receives frames of data and commands. Transmit and receive protocol engine is controlled by host driver software which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.

摘要翻译： 通信处理器发送和接收数据帧和数据帧。 发送和接收协议引擎由主机驱动程序软件控制，主机驱动程序使用预定位来指示哪一帧是一系列帧中的最后一帧。 然后将该信息发送到发送帧之前。

公开(公告)号：US06314100B1

公开(公告)日：2001-11-06

申请号：US09048930

申请日：1998-03-26

申请人： Bradley Roach ,  Stuart Berman ,  David Duckman

发明人： Bradley Roach ,  Stuart Berman ,  David Duckman

IPC分类号： H04L1256

CPC分类号： H04L49/901 ,  H04L49/357 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9094

摘要： A method of validation and host buffer allocation for unmapped fiber channel frames. More particularly, the invention encompasses a method of validating unmapped frames, each including a header and a payload, including receiving a frame as a current frame; determining if the current frame is a first frame in a sequence, and if so, saving the header and payload of the current frame in a buffer, and otherwise determining if the current frame is a next expected frame in the sequence; if the current frame is the next expected frame in the sequence, then saving the payload of the current frame in the buffer after the payload of the prior frame; determining if the current frame is a last frame in the sequence, and if so, sending a message to a host indicating receipt of the complete sequence; if the current frame is not the next expected frame in the sequence, then saving the header and payload of the current frame in the buffer, and sending a message to the host indicating receipt of a partial sequence. The host CPU is interrupted when either a complete sequence is received, or a partial sequence is received, followed by a frame from a different sequence. The host CPU may then process the concatenated payload of the sequence. The invention is particularly useful for processing TCP/IP frames in a Fiber Channel network.

摘要翻译： 一种用于未映射光纤通道帧的验证方法和主机缓冲区分配方法。 更具体地，本发明包括验证未映射帧的方法，每个帧包括报头和有效载荷，包括接收帧作为当前帧; 确定当前帧是否是序列中的第一帧，如果是，则将当前帧的报头和有效载荷保存在缓冲器中，否则确定当前帧是否是序列中的下一个预期帧; 如果当前帧是序列中的下一个预期帧，则将当前帧的有效载荷在先前帧的有效载荷之后保存在缓冲器中; 确定当前帧是否是序列中的最后一帧，如果是，则向主机发送指示接收到完整序列的消息; 如果当前帧不是序列中的下一个预期帧，则将当前帧的报头和有效载荷保存在缓冲器中，并向主机发送指示接收到部分序列的消息。 当接收到完整的序列或接收到部分序列后，主机CPU被中断，后面是来自不同序列的帧。 然后，主机CPU可以处理序列的级联有效载荷。 本发明对于在光纤通道网络中处理TCP / IP帧特别有用。

公开(公告)号：US20070067534A1

公开(公告)日：2007-03-22

申请号：US11228862

申请日：2005-09-16

申请人： Jim Butler ,  Michael Jordan ,  Joe Tien ,  David Duckman

发明人： Jim Butler ,  Michael Jordan ,  Joe Tien ,  David Duckman

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.

摘要翻译： 公开了一种用于通过实现用于中断条件的有效递送和清除机制来提高MSI和MSI-X规范以提高驱动器和硬件/固件接口之间的性能同时确保在该过程中不会中断丢失的方法和装置。 特别地，采用自动清除功能来消除对主机中的驱动程序的需求，以通过基于PCI的总线发送写入，以断言并声明注意使能寄存器位并清除注意事件寄存器位，并且使用故障安全机制 防止丢失中断。

公开(公告)号：US20060123160A1

公开(公告)日：2006-06-08

申请号：US11004346

申请日：2004-12-03

申请人： David Duckman ,  Gregory Scherer

发明人： David Duckman ,  Gregory Scherer

IPC分类号： G06F3/06

CPC分类号： G06F9/4812

摘要： An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface port. The interrupt notification block is written by the host interface port and pre-fixed into the port pointer array of a host at the time the host interface port updates the pointers stored in a port pointer array in host memory. The host may then read the interrupt notification block to determine how to process a response or an interrupt rather than having to read the host attention register in the host interface port across the host bus.

摘要翻译： 公开了存储在主机存储器中的中断通知块，其包含可存储在主机接口端口中的主机注意寄存器中的中断条件内容的映像。 中断通知块由主机接口端口写入，并在主机接口端口更新存储在主机内存中的端口指针数组中的指针时，将其预固定到主机的端口指针数组中。 然后，主机可以读取中断通知块，以确定如何处理响应或中断，而不必在主机总线上的主机接口端口中读取主机注意寄存器。

公开(公告)号：US20050066080A1

公开(公告)日：2005-03-24

申请号：US10668138

申请日：2003-09-22

申请人： David Duckman

发明人： David Duckman

IPC分类号： G06F9/46 ,  H04L29/08 ,  G06F3/00

CPC分类号： G06F9/546 ,  H04L67/1097 ,  H04L69/329

摘要： Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectivity in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.

摘要翻译： 公开了与广义队列相关联的广义队列和专用寄存器，用于协调两个紧密耦合的处理器之间的信息传递。 可以调整队列的容量以匹配当前的环境，对发送和接收处理器之间商定的条目的大小没有限制，对于条目出现的条目数量或限制条件没有实际限制 。 此外，专用寄存器允许立即通知队列和其他条件，接收和生成条件的选择性，以及将数据传输和特定条件通知组合在同一关注寄存器中的能力。

公开(公告)号：US20050050245A1

公开(公告)日：2005-03-03

申请号：US10651887

申请日：2003-08-29

申请人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Daming Jin ,  John Tang

发明人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Daming Jin ,  John Tang

IPC分类号： G06F20060101 ,  G06F13/28 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F13/28

摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.

摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。

公开(公告)号：US20060161733A1

公开(公告)日：2006-07-20

申请号：US11039446

申请日：2005-01-19

申请人： Jeffrey Beckett ,  David Duckman ,  Alexander Nicolson ,  William Qi ,  Michael Jordan

发明人： Jeffrey Beckett ,  David Duckman ,  Alexander Nicolson ,  William Qi ,  Michael Jordan

IPC分类号： G06F12/14 ,  G06F13/28

CPC分类号： G06F13/4059

摘要： The preferred embodiment of present invention is directed to an improved method and system for buffering incoming/unsolicited data received by a host computer that is connected to a network such as a storage area network. Specifically, in a host computer system in which the main memory of the host server maintains a I/O control block command ring, and which a connective port (e.g., a host bus adaptor) is operatively coupled to the main memory for handling I/O commands received by and transmitted from the host server, a host buffer queue (HBQ) is maintained for storing a series of buffer descriptors retrievable by the port for writing incoming/unsolicited data to specific address locations within the main memory. In an alternative embodiment of the present invention, multiple HBQs are maintained for storing buffer entries dedicated to different types and/or lengths of data, where each of the HBQ can be separately configured to contain a selection profile describing the specific type of data for which the HBQ is dedicated to service.

摘要翻译： 本发明的优选实施例涉及一种改进的方法和系统，用于缓冲由连接到诸如存储区域网络的网络的主计算机接收的进入/未经请求的数据。 具体地说，在其中主机服务器的主存储器维护I / O控制块命令环，并且连接端口（例如，主机总线适配器）可操作地耦合到主存储器以用于处理I / O控制块命令环的主计算机系统中， 由主机服务器接收和发送的O命令，主机缓冲器队列（HBQ）被维护，用于存储由端口检索的一系列缓冲器描述符，用于将传入/非请求数据写入主存储器内的特定地址位置。 在本发明的替代实施例中，保持多个HBQ用于存储专用于不同类型和/或数据长度的缓冲器条目，其中HBQ中的每一个可以被单独配置成包含描述特定类型的数据的选择简档， HBQ致力于服务。

公开(公告)号：US20050050283A1

公开(公告)日：2005-03-03

申请号：US10651890

申请日：2003-08-29

申请人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Khanh Huynh

发明人： Eddie Miller ,  David Duckman ,  Jim Butler ,  Khanh Huynh

IPC分类号： G06F20060101 ,  G06F12/00

CPC分类号： G06F9/526

摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

摘要翻译： 一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。 在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性 和时机。