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    Method and system for using dynamic random access memory as cache memory
    1.
    发明申请
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US20080177943A1

    公开(公告)日：2008-07-24

    申请号：US12069812

    申请日：2008-02-12

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Method and system for using dynamic random access memory as cache memory
    2.
    发明授权
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US07350018B2

    公开(公告)日：2008-03-25

    申请号：US11595370

    申请日：2006-11-08

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    IPC分类号： G06F12/16

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体中读取的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Method and system for using dynamic random access memory as cache memory
    3.
    发明授权
    Method and system for using dynamic random access memory as cache memory 失效
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US06862654B1

    公开(公告)日：2005-03-01

    申请号：US09642546

    申请日：2000-08-17

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    IPC分类号： G11C7/10 ,  G11C11/406 ,  G11C11/409 ,  G11C15/04 ,  G06F12/00

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Method and system for hiding refreshes in a dynamic random access memory
    4.
    发明授权
    Method and system for hiding refreshes in a dynamic random access memory 有权
    用于在动态随机存取存储器中隐藏刷新的方法和系统

    公开(公告)号：US06445636B1

    公开(公告)日：2002-09-03

    申请号：US09641881

    申请日：2000-08-17

    申请人： Brent Keeth ,  Brian M. Shirley ,  Kevin J. Ryan ,  Charles H. Dennison

    发明人： Brent Keeth ,  Brian M. Shirley ,  Kevin J. Ryan ,  Charles H. Dennison

    IPC分类号： G11C700

    CPC分类号： G11C11/40618 ,  G11C7/1042 ,  G11C11/406

    摘要： A method and system for refreshing a dynamic random access memory (“DRAM”) includes a pair of memory arrays for each of a plurality of banks. The DRAM includes the usual addressing and data path circuitry, as well as a refresh controller that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM can be used in place of an SRAM as a cache memory. Since only one of the arrays in each bank is refreshed at a time, the refresh controller is able to allow data to be written to the array that is not being refreshed. The refresh controller then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.

    摘要翻译： 用于刷新动态随机存取存储器（“DRAM”）的方法和系统包括用于多个存储体中的每一个的一对存储器阵列。 DRAM包括通常的寻址和数据路径电路，以及刷新控制器，其以隐藏更充分的方式刷新阵列，使得DRAM可以用来代替SRAM作为高速缓冲存储器。 由于每次刷新每个存储体中只有一个阵列，所以刷新控制器能够将数据写入未刷新的数组。 然后，刷新控制器使得写入数据被临时存储，使得其可以被写入阵列的刷新的阵列已经完成。 如果两个数组都不被刷新，数据将被写入两个数组。 通过首先检查来确定数组是否被刷新，从数组中读取数据。 如果是这样，数据从数组中读取，没有被刷新。

    Method and system for using dynamic random access memory as cache memory
    5.
    发明授权
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US07917692B2

    公开(公告)日：2011-03-29

    申请号：US12069812

    申请日：2008-02-12

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Method and system for using dynamic random access memory as cache memory
    7.
    发明授权
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US07155561B2

    公开(公告)日：2006-12-26

    申请号：US11230836

    申请日：2005-09-19

    申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison

    发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison

    IPC分类号： G06F12/16

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

    Integrated circuit power supply having piecewise linearity
    8.
    发明授权
    Integrated circuit power supply having piecewise linearity 失效
    具有分段线性的集成电路电源

    公开(公告)号：US5552739A

    公开(公告)日：1996-09-03

    申请号：US559414

    申请日：1995-11-15

    申请人： Brent Keeth ,  Paul S. Zagar ,  Brian M. Shirley ,  Stephen L. Casper

    发明人： Brent Keeth ,  Paul S. Zagar ,  Brian M. Shirley ,  Stephen L. Casper

    IPC分类号： G05F1/46 ,  G05F1/10

    CPC分类号： G05F1/465

    摘要： A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry. When used in a dynamic random access memory integrated circuit, operation in the first segment provides data retention at low power consumption. Operation in the second segment supports speed grading individual devices with a margin for properly stating memory performance specifications. Operation in the third segment supports screening at elevated temperatures for identifying weak and defective memory devices.

    摘要翻译： 集成电路的电源具有分段线性工作特性，用于改进的集成电路测试和屏蔽。 接收外部施加的电源信号（指定为VCCX）的集成电路中，包括用于产生内部工作电压的电源（指定为VCCR），片上电源电路提供VCCR作为VCCX的分段线性功能。 在这种功能的第一段中，VCCR逼近VCCX以实现有效的低电压操作。 在用于集成电路的正常操作的第二段中，VCCR随着VCCX逐渐上升，从而可以保证测量公差，工艺变化和降额的边缘上的测试结果。 在第三部分中，VCCR在预定的常数偏移下遵循VCCX以下。 由于电源电路中使用的非线性器件，片段之间的转换是平滑的。 当在动态随机存取存储器集成电路中使用时，第一段中的操作以低功耗提供数据保持。 第二部分中的操作支持对具有裕量的各个设备进行速度分级，以正确说明内存性能规格。 第三部分的操作支持在升高的温度下进行筛选以识别弱和有缺陷的存储器件。