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    Communication system and encoding method having low overhead
    1.
    发明授权
    Communication system and encoding method having low overhead 有权
    具有低开销的通信系统和编码方法

    公开(公告)号：US07809021B2

    公开(公告)日：2010-10-05

    申请号：US11431929

    申请日：2006-05-09

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H04J3/00

    CPC classification number: H04L69/22 ,  H04J3/06 ,  H04J3/0602 ,  H04J3/1617 ,  H04J3/1658 ,  H04L1/0041 ,  H04L25/03057

    Abstract: A communication system processes blocks of input data that include control words and a packet of information words are received. The packet has a start preceded by ones of the control words and an end followed by others of the control words. When the block consists exclusively of information words, a one bit block header having a first sense is appended to the block to form a frame. When the block does not consist exclusively of information words, the block is condensed to accommodate a TYPE word, the TYPE word is generated and inserted into the block and a one bit block header is appended to the block to form the frame. When the block does not consist exclusively of information words the one bit block header has a second sense, opposite to the first sense. Use of a one bit block header reduces overhead. Forward error correction is also utilized.

    Abstract translation: 通信系统处理包含控制字和信息字包的输入数据块。 分组具有一个控制字前面的开始，另一个控制字后面跟着一个。 当该块仅由信息字组成时，具有第一感测的一位块标题被附加到该块以形成一帧。 当块不仅仅由信息字组成时，块被压缩以容纳TYPE字，产生TYPE字并将其插入到块中，并且将一个位块标头附加到块以形成帧。 当块不仅仅由信息字组成时，一比特块头具有与第一感觉相反的第二感测。 使用一个位块头减少开销。 还使用前向纠错。

    Method and system for a multi-rate gigabit media independent interface
    2.
    发明授权
    Method and system for a multi-rate gigabit media independent interface 有权
    用于多速率千兆位媒体独立接口的方法和系统

    公开(公告)号：US07720068B2

    公开(公告)日：2010-05-18

    申请号：US11894990

    申请日：2007-08-21

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H04L12/56

    CPC classification number: H04L47/10 ,  H04L27/0008 ,  H04L47/22 ,  H04L2212/00

    Abstract: Disclosed is a UGMII system to interface multirate devices including 10 gigabit per second data exchange rates. Mode selection is enabled to provide for automatic detection and adaptation to any transmit rate including 10M, 100M, 1G, and 10G. Mode selection comprises the negotiation between the UGMII extension sublayers located at the MAC and PHY to select between one of several operational modes including: XGMII communication, GMII encapsulation, Clause 22 MDIO register management and Clause 45 MDIO register management. Selection of UGMII and XGMII operating modes are negotiated between the MAC and PHY using ordered sets to announce and acknowledgement a mode change. In one embodiment 802.3 Clause 46 defined ordered sets are utilized.

    Abstract translation: 公开了一种用于接口多速率设备的UGMII系统，包括10吉比特每秒的数据交换率。 启用模式选择以提供对包括10M，100M，1G和10G的任何传输速率的自动检测和自适应。 模式选择包括位于MAC和PHY之间的UGMII扩展子层之间的协商，以在几种操作模式之一之间进行选择，包括：XGMII通信，GMII封装，第22章MDIO寄存器管理和第45条MDIO寄存器管理。 使用有序集合在MAC和PHY之间协商UGMII和XGMII操作模式的选择，以通知和确认模式更改。 在一个实施例中，使用802.3第46条定义的有序集。

    Method and system for a multi-rate gigabit media independent interface
    3.
    再颁专利
    Method and system for a multi-rate gigabit media independent interface 有权

    公开(公告)号：USRE46523E1

    公开(公告)日：2017-08-22

    申请号：US13474515

    申请日：2012-05-17

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H04L27/00 ,  H04L12/815 ,  H04J3/24 ,  H04L12/801

    CPC classification number: H04L47/10 ,  H04L27/0008 ,  H04L47/22 ,  H04L2212/00

    Abstract: Disclosed is a UGMII system to interface multirate devices including 10 gigabit per second data exchange rates. Mode selection is enabled to provide for automatic detection and adaptation to any transmit rate including 10M, 100M, 1G, and 10G. Mode selection comprises the negotiation between the UGMII extension sublayers located at the MAC and PHY to select between one of several operational modes including: XGMII communication, GMII encapsulation, Clause 22 MDIO register management and Clause 45 MDIO register management. Selection of UGMII and XGMII operating modes are negotiated between the MAC and PHY using ordered sets to announce and acknowledgement a mode change. In one embodiment 802.3 Clause 46 defined ordered sets are utilized.

    Runlength-limited code and method
    4.
    发明授权
    Runlength-limited code and method 有权
    运行长度限制代码和方法

    公开(公告)号：US06285302B1

    公开(公告)日：2001-09-04

    申请号：US09464654

    申请日：1999-12-15

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H03M700

    CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1446 ,  G11B2020/1449

    Abstract: A method to create runlength-limited codes from shorter codes having suppression of error propagation by insertion of uncoded bits adjacent error suppression end bits of the shorter code.

    Abstract translation: 一种通过插入与较短代码的差错抑制结束位相邻的未编码位来抑制误差传播的较短代码创建游程长度限制代码的方法。

    Multi-rate media independent interface over a physical coding sublayer
    5.
    发明授权
    Multi-rate media independent interface over a physical coding sublayer 有权
    物理编码子层上的多速率媒体独立接口

    公开(公告)号：US08885664B1

    公开(公告)日：2014-11-11

    申请号：US13591954

    申请日：2012-08-22

    Applicant: William Lo ,  Brett A. McClellan

    Inventor： William Lo ,  Brett A. McClellan

    IPC: H04W4/00 ,  H04J3/18

    CPC classification number: H04L12/28 ,  H04J3/18 ,  H04L1/00 ,  H04L1/08 ,  H04L12/413 ,  H04L25/05

    Abstract: A method for converting a data stream from a first rate to a second rate NA times greater than the first rate, such that the converted data stream conforms to a coding requirement that symbols be arranged in units of symbol length M, includes receiving, at the first rate, a data packet, and an inter-packet gap containing Y1 idle symbols, generating NA repetitions of each data symbol of the data packet, determining whether replicating each symbol of the inter-packet gap NA times would violate the coding requirement, and, at least partially in response to determining that replicating each symbol of the inter-packet gap NA times would violate the requirement, generating greater than or less than Y1*NA idle symbols. The method also includes outputting, at the second rate, the generated NA repetitions of each data symbol and the generated idle symbols.

    Abstract translation: 一种用于将数据流从第一速率转换为大于第一速率NA的第二速率的方法，使得转换的数据流符合符号以符号长度M为单位排列的编码要求，包括在 第一速率，数据分组和包含Y1空闲符号的分组间间隔，产生数据分组的每个数据符号的NA重复，确定是否复制分组间间隙NA的每个符号将违反编码要求，以及 至少部分地响应于确定复制每个分组间间隙的每个符号NA次将违反要求，生成大于或小于Y1 * NA空闲符号。 该方法还包括以第二速率输出每个数据符号的所生成的NA重复和产生的空闲符号。

    Communication system and encoding method having low overhead
    6.
    发明授权
    Communication system and encoding method having low overhead 有权
    具有低开销的通信系统和编码方法

    公开(公告)号：US08472478B2

    公开(公告)日：2013-06-25

    申请号：US12924565

    申请日：2010-09-28

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H04J3/00

    CPC classification number: H04L69/22 ,  H04J3/06 ,  H04J3/0602 ,  H04J3/1617 ,  H04J3/1658 ,  H04L1/0041 ,  H04L25/03057

    Abstract: A communication system processes blocks of input data that include control words and a packet of information words are received. The packet has a start preceded by ones of the control words and an end followed by others of the control words. When the block consists exclusively of information words, a one bit block header having a first sense is appended to the block to form a frame. When the block does not consist exclusively of information words, the block is condensed to accommodate a TYPE word, the TYPE word is generated and inserted into the block and a one bit block header is appended to the block to form the frame. When the block does not consist exclusively of information words the one bit block header has a second sense, opposite to the first sense. Use of a one bit block header reduces overhead. Forward error correction is also utilized.

    Abstract translation: 通信系统处理包含控制字和信息字包的输入数据块。 分组具有一个控制字前面的开始，另一个控制字后面跟着一个。 当该块仅由信息字组成时，具有第一感测的一位块标题被附加到该块以形成一帧。 当块不仅仅由信息字组成时，块被压缩以容纳TYPE字，产生TYPE字并将其插入到块中，并且将一个位块标头附加到块以形成帧。 当块不仅仅由信息字组成时，一比特块头具有与第一感觉相反的第二感测。 使用一个位块头减少开销。 还使用前向纠错。

    Multi-rate media independent interface over a physical coding sublayer
    7.
    发明授权
    Multi-rate media independent interface over a physical coding sublayer 有权
    物理编码子层上的多速率媒体独立接口

    公开(公告)号：US08873579B1

    公开(公告)日：2014-10-28

    申请号：US13591974

    申请日：2012-08-22

    Applicant: William Lo ,  Brett A. McClellan

    Inventor： William Lo ,  Brett A. McClellan

    IPC: H04W4/00 ,  H04L12/28 ,  H04J3/18

    CPC classification number: H04L12/28 ,  H04J3/18 ,  H04L1/00 ,  H04L1/08 ,  H04L12/413 ,  H04L25/05

    Abstract: A method for inserting ordered sets into a data stream converted from a first rate to a second rate NA times greater than the first rate, while conforming to a requirement that symbols be arranged in units of symbol length M, includes receiving, at the first rate, a data packet containing data symbols, receiving Y1 symbols of control information, and identifying an ordered set based on the Y1 symbols. The method also includes generating NA repetitions of each data symbol of the data packet, determining whether Y1*NA/M has a non-zero remainder, and, at least partially in response to determining that Y1*NA/M has a non-zero remainder, generating a number of repetitions of the ordered set containing either more or fewer than Y1*NA symbols. The method also includes outputting, at the second rate, the data symbol repetitions and first ordered set repetitions.

    Abstract translation: 一种用于将顺序集合插入到从第一速率转换成大于第一速率NA的第二速率的数据流的方法，同时符合符号以符号长度M为单位排列的要求，包括以第一速率接收 包含数据符号的数据分组，接收控制信息的Y1个符号，以及基于Y1符号识别有序集合。 该方法还包括产生数据分组的每个数据符号的NA重复，确定Y1 * NA / M是否具有非零余数，并且至少部分地响应于确定Y1 * NA / M具有非零 余数，产生包含多于或少于Y1 * NA符号的有序集合的重复次数。 该方法还包括以第二速率输出数据符号重复和首次设置重复。

    Communication system and encoding method having low overhead
    8.
    发明申请
    Communication system and encoding method having low overhead 有权
    具有低开销的通信系统和编码方法

    公开(公告)号：US20110075683A1

    公开(公告)日：2011-03-31

    申请号：US12924565

    申请日：2010-09-28

    Applicant: Brett A. McClellan

    Inventor： Brett A. McClellan

    IPC: H04J3/24

    CPC classification number: H04L69/22 ,  H04J3/06 ,  H04J3/0602 ,  H04J3/1617 ,  H04J3/1658 ,  H04L1/0041 ,  H04L25/03057

    Abstract: A communication system processes blocks of input data that include control words and a packet of information words are received. The packet has a start preceded by ones of the control words and an end followed by others of the control words. When the block consists exclusively of information words, a one bit block header having a first sense is appended to the block to form a frame. When the block does not consist exclusively of information words, the block is condensed to accommodate a TYPE word, the TYPE word is generated and inserted into the block and a one bit block header is appended to the block to form the frame. When the block does not consist exclusively of information words the one bit block header has a second sense, opposite to the first sense. Use of a one bit block header reduces overhead. Forward error correction is also utilized.

    Abstract translation: 通信系统处理包含控制字和信息字包的输入数据块。 分组具有一个控制字前面的开始，另一个控制字后面跟着一个。 当该块仅由信息字组成时，具有第一感测的一位块标题被附加到该块以形成一帧。 当块不仅仅由信息字组成时，块被压缩以容纳TYPE字，产生TYPE字并将其插入到块中，并且将一个位块标头附加到块以形成帧。 当块不仅仅由信息字组成时，一比特块头具有与第一感觉相反的第二感测。 使用一个位块头减少开销。 还使用前向纠错。

    Pin layer reversal detection
    9.
    发明授权
    Pin layer reversal detection 有权
    针层反转检测

    公开(公告)号：US06909567B2

    公开(公告)日：2005-06-21

    申请号：US10053394

    申请日：2001-10-29

    Applicant: Brett A. McClellan ,  Zubir Adal

    Inventor： Brett A. McClellan ,  Zubir Adal

    IPC: G11B5/00 ,  G11B5/596 ,  G11B19/04 ,  G11B20/10 ,  G11B27/30 ,  G11B5/09

    CPC classification number: B82Y10/00 ,  G11B5/59616 ,  G11B5/5965 ,  G11B5/59683 ,  G11B19/04 ,  G11B20/10009 ,  G11B27/3027 ,  G11B2005/0008 ,  G11B2005/0016 ,  G11B2220/20

    Abstract: A circuit to detect pin layer reversal including an input circuit to receive an input signal having a first portion to indicate a pin layer reversal and having a second portion to indicate a servo sync mark, a first servo sync mark detector for detecting a positive servo sync mark from the input signal, a second servo sync mark detector for detecting a negative servo sync mark from the input signal, and a circuit responsive to the positive servo sync mark and the negative servo sync mark to generate a signal to indicate if the servo sync mark has been reversed and to generate a signal to indicate the pin layer reversal.

    Abstract translation: 一种用于检测引脚层反转的电路，包括输入电路以接收具有第一部分的输入信号，以指示引脚层反转并具有指示伺服同步标记的第二部分;第一伺服同步标记检测器，用于检测正伺服同步 从输入信号标记的第二伺服同步标记检测器，用于从输入信号检测负伺服同步标记的第二伺服同步标记检测器，以及响应于正伺服同步标记和负伺服同步标记的电路，以产生信号以指示伺服同步 标记被反转，并产生一个信号以指示针层反转。

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