利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.027 秒)

    I/O configuration and reconfiguration trigger through testing interface
    1.
    发明授权
    I/O configuration and reconfiguration trigger through testing interface 有权
    通过测试界面进行I / O配置和重新配置触发

    公开(公告)号：US07287189B1

    公开(公告)日：2007-10-23

    申请号：US10603888

    申请日：2003-06-25

    申请人： Brian D. Johnson ,  Keith Duwel ,  Mario Guzman ,  Christopher F. Lane ,  Andy L. Lee

    发明人： Brian D. Johnson ,  Keith Duwel ,  Mario Guzman ,  Christopher F. Lane ,  Andy L. Lee

    IPC分类号： G06F11/00

    CPC分类号： G01R31/318572

    摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.

    摘要翻译： 可重构设备在测试期间从诊断接口加载I / O配置信息。 该设备包括用于与其他设备通信值的可配置I / O连接。 诊断接口将I / O连接的值传送给测试仪。 设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式 接口，从而修改I / O连接的配置。 该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。 响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。 诊断接口可以是JTAG接口。

    Reconfigurable programmable logic system with configuration recovery mode
    2.
    发明授权
    Reconfigurable programmable logic system with configuration recovery mode 有权
    具有配置恢复模式的可重构可编程逻辑系统

    公开(公告)号：US07512849B1

    公开(公告)日：2009-03-31

    申请号：US11294715

    申请日：2005-12-05

    申请人： Tim Allen ,  Michael Fairman ,  Mario Guzman ,  Bryan Hoyer ,  Chris Lane ,  Kerry Veenstra ,  Keith Duwel ,  Andy L. Lee

    发明人： Tim Allen ,  Michael Fairman ,  Mario Guzman ,  Bryan Hoyer ,  Chris Lane ,  Kerry Veenstra ,  Keith Duwel ,  Andy L. Lee

    IPC分类号： G01R31/28 ,  G06F7/38

    CPC分类号： G01R31/318516

    摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

    摘要翻译： 可编程逻辑系统包括可重新配置的可编程逻辑器件和存储至少两种配置的配置存储器。 首先加载默认配置，然后加载所需的用户应用程序配置。 如果用户应用程序配置失败，系统将保存有关故障的数据，然后返回到默认配置进行恢复。 读取故障数据后，默认配置会导致调用操作员进行干预，或者在配置存储器中可用时加载不同的（例如，以前的）配置。 该系统在用户可以远程更新配置的情况下特别有用。 在另一种模式下，系统仅存储用户配置（首先被加载）和默认配置。 如果新加载的配置失败，则加载默认配置，并向操作员发出信号，或者在加载不同配置时采取其他操作。

    Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
    4.
    发明授权
    Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
    可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器

    公开(公告)号：US07705628B1

    公开(公告)日：2010-04-27

    申请号：US11486164

    申请日：2006-07-12

    申请人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

    发明人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

    IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094 ,  H01L25/00

    CPC分类号： H03K19/173 ,  H03K19/1736 ,  H03K19/17728

    摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

    摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

    Integrated circuits with configurable initialization data memory addresses
    6.
    发明授权
    Integrated circuits with configurable initialization data memory addresses 失效
    具有可配置初始化数据存储器地址的集成电路

    公开(公告)号：US07702893B1

    公开(公告)日：2010-04-20

    申请号：US11525657

    申请日：2006-09-22

    申请人： Nicholas J. Rally ,  Dirk A. Reese ,  Keith Duwel

    发明人： Nicholas J. Rally ,  Dirk A. Reese ,  Keith Duwel

    IPC分类号： G06F15/177

    CPC分类号： G06F9/4401

    摘要： Systems and methods are provided for avoiding memory address conflicts in systems containing shared memory. Upon system power up, programmable logic device integrated circuits, microprocessors, and other integrated circuits with processing capabilities are provided with unique initialization data memory addresses. Each unique initialization data memory address corresponds to a respective non-overlapping block of memory in the shared memory. During initialization operations, the integrated circuits retrieve initialization data from the shared memory using the unique initialization data memory addresses. The integrated circuits can be organized using a master-slave architecture. The master can load the initialization data memory addresses into the slave integrated circuits using communications circuitry that is active after the slaves have powered up but before the slaves have been initialized.

    摘要翻译： 提供了系统和方法，用于避免包含共享内存的系统中的内存地址冲突。 在系统上电时，可编程逻辑器件集成电路，微处理器和具有处理能力的其他集成电路提供唯一的初始化数据存储器地址。 每个唯一的初始化数据存储器地址对应于共享存储器中相应的不重叠的存储器块。 在初始化操作期间，集成电路使用唯一的初始化数据存储器地址从共享存储器检索初始化数据。 可以使用主从架构来组织集成电路。 主机可以使用通信电路将初始化数据存储器地址加载到从属集成电路中，这些通信电路在从机通电之后，但在从站已初始化之前处于活动状态。

    Apparatus and methods for controlled error injection
    9.
    发明授权
    Apparatus and methods for controlled error injection 有权
    用于控制误差注入的装置和方法

    公开(公告)号：US08650447B1

    公开(公告)日：2014-02-11

    申请号：US13183147

    申请日：2011-07-14

    申请人： Curt Wortman ,  Keith Duwel ,  Huy Ngo

    发明人： Curt Wortman ,  Keith Duwel ,  Huy Ngo

    IPC分类号： G01R31/28 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/54 ,  G01R31/318516 ,  G11C29/04

    摘要： In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.

    摘要翻译： 根据本发明的实施例，错误注入的精确控制可以通过伴随数据路径的各个流水线级数据传输的同步误差信号来实现。 同步误差信号可用于触发给定协议逻辑块（即在数据路径的给定子组件中）的错误事件。 协议逻辑块是可配置的，以确定是否在断言错误信号时采取任何动作。 随着数据信号（及其伴随的同步误差信号）通过数据路径的流水线功能，可能会触发多个错误事件，从而创建复杂的错误条件。 此外，可以使用在正向和反向转换两者上具有可旁路块的环回路径来实现所创建的错误的确定性处理。 还公开了其它实施例，方面和特征。