公开(公告)号：US09122832B2

公开(公告)日：2015-09-01

申请号：US12512932

申请日：2009-07-30

申请人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

发明人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并且随后从晶片中移除留下期望的永久结构。

公开(公告)号：US08225239B2

公开(公告)日：2012-07-17

申请号：US12479674

申请日：2009-06-05

申请人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks ,  Scott T. Becker

发明人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks ,  Scott T. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

摘要翻译： 正常的布局形状根据虚拟炉排放置。 确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。 在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。 此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。 子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。

公开(公告)号：US20090300574A1

公开(公告)日：2009-12-03

申请号：US12479674

申请日：2009-06-05

申请人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks

发明人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

摘要翻译： 正常的布局形状根据虚拟炉排放置。 确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。 在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。 此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。 子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。

公开(公告)号：US20100031211A1

公开(公告)日：2010-02-04

申请号：US12512932

申请日：2009-07-30

申请人： Brian Reed ,  Michael C. Smayling

发明人： Brian Reed ,  Michael C. Smayling

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并随后从晶片上移除留下期望的永久结构。

公开(公告)号：US06924687B2

公开(公告)日：2005-08-02

申请号：US10630949

申请日：2003-07-29

申请人： Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam ,  Scott T. Becker

发明人： Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam ,  Scott T. Becker

IPC分类号： H03K19/003 ,  H03L5/00

CPC分类号： H03K19/00315

摘要： An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a VDD voltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.

摘要翻译： 公开了一种用于保护输入缓冲器的发明。 当输入缓冲器的输入电压容限为高电平时，从p电源到输入缓冲器的电流降低。 p电源是提供给输入缓冲器中的p沟道晶体管的V DD电压。 此外，当输入缓冲器的输入电压为低电平时，p电源被设置为特定电压，特定电压处于特定值，使得输入缓冲器内的输入晶体管不经历过应力电压。 可选地，当输入缓冲器的输入电压容限为高电平时，可以防止p电源向输入缓冲器提供电流。

公开(公告)号：US08448102B2

公开(公告)日：2013-05-21

申请号：US12481445

申请日：2009-06-09

申请人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed ,  Scott T. Becker

发明人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed ,  Scott T. Becker

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： H01L23/528 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

摘要翻译： 在动态阵列结构中，通过在不规则布线区域的第一和第二侧上分别放置第一和第二规则布线形状来将芯片级布局的一部分内的不规则布线布局区域包围。 一个或多个不规则的线布局形状放置在不规则布线区域内。 在第一规则布线形状和最接近第一规则布线形状的不规则布线区域内的第一外部不规则布线布局形状之间保持第一边缘间隔。 在第二规则布线形状和最接近第二规则布线形状的不规则布线区域内的第二外部不规则布线布局形状之间保持第二边缘间隔。 第一和第二边缘间距被限定以优化规则和不规则布线形状的光刻。

公开(公告)号：US07005910B2

公开(公告)日：2006-02-28

申请号：US10759339

申请日：2004-01-16

申请人： Scott T. Becker ,  Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam

发明人： Scott T. Becker ,  Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam

IPC分类号： H03K17/04

CPC分类号： H03K19/01707

摘要： An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

摘要翻译： 提供了一种用于减少通过反相电路的延迟的前馈电路的发明。 前馈电路包括具有输入和输出的反相器和具有输入和输出的反相电路。 反相电路的输入耦合到逆变器的输出端。 还包括具有耦合到反相器的输入端的栅极和耦合到反相电路的输出的端子的前馈晶体管。 在操作中，前馈晶体管减小了反相电路的输出改变状态所需的时间量。 总之，本发明减小了当反相电路转变到高电平状态时的延迟，而不会影响转换到低电平的时序。

公开(公告)号：US10435316B2

公开(公告)日：2019-10-08

申请号：US13247138

申请日：2011-09-28

申请人： Brian Reed ,  Carla Dillon

发明人： Brian Reed ,  Carla Dillon

IPC分类号： C02F1/52 ,  C02F1/66 ,  C02F1/72 ,  C02F101/10

摘要： Compositions for the use of sewage or wastewater treatment, controlling odors or a combination thereof are disclosed, wherein the composition comprises at least one iron-based compound. Furthermore, methods of reducing the odors in a sewage or wastewater system are disclosed that include: adding a composition comprising at least one iron-based compound to a sewage or wastewater system. As used herein, the phrase “at least one iron-based compound” includes ferrous chloride, ferric chloride, ferrous sulfate, ferrate, polyferric sulfate, Ferix-3 (Fe2(SO4)3H2O) or a combination thereof.

公开(公告)号：US20140201772A1

公开(公告)日：2014-07-17

申请号：US14217039

申请日：2014-03-17

申请人： Zeev Neumeier ,  Brian Reed

发明人： Zeev Neumeier ,  Brian Reed

IPC分类号： H04N21/442

CPC分类号： H04N21/44008 ,  G06F17/30017 ,  H04N5/44591 ,  H04N5/765 ,  H04N9/8205 ,  H04N21/235 ,  H04N21/2353 ,  H04N21/236 ,  H04N21/23614 ,  H04N21/2401 ,  H04N21/435 ,  H04N21/44204 ,  H04N21/44213 ,  H04N21/44222 ,  H04N21/4424 ,  H04N21/4532 ,  H04N21/462 ,  H04N21/4667 ,  H04N21/478 ,  H04N21/6581 ,  H04N21/6582 ,  H04N21/812 ,  H04N21/8126 ,  H04N21/8133

摘要： A system, method and computer program utilize a distance associative hashing algorithmic means to provide a highly efficient means to rapidly address a large database. The indexing means can be readily subdivided into a plurality of independently-addressable segments where each such segment can address a portion of related data of the database where the sub-divided indexes of said portions reside entirely in the main memory of each of a multiplicity of server means. The resulting cluster of server means, each hosting an addressable sector of a larger database of searchable audio or video information, provides a significant improvement in the latency and scalability of an Automatic Content Recognition system, among other uses.

摘要翻译： 一种系统，方法和计算机程序利用距离关联散列算法的手段来提供一种快速解决大型数据库的高效手段。 索引装置可以容易地被细分成多个可独立寻址的段，其中每个这样的段可以解决数据库的相关数据的一部分，其中所述部分的分分割索引完全驻留在多个 服务器方式。 所产生的服务器集群意味着每个主机可搜索音频或视频信息的较大数据库的可寻址扇区，提供自动内容识别系统的延迟和可扩展性的显着改进以及其他用途。

公开(公告)号：US20120141407A1

公开(公告)日：2012-06-07

申请号：US13247138

申请日：2011-09-28

申请人： Carla Dillon ,  Brian Reed ,  Talebi Mahin

发明人： Carla Dillon ,  Brian Reed ,  Talebi Mahin

IPC分类号： C02F1/68 ,  C01G49/14 ,  C01G49/00 ,  C01G49/10

CPC分类号： C02F1/5245 ,  C02F1/66 ,  C02F1/722 ,  C02F2101/101 ,  C02F2303/02 ,  C02F2307/08

摘要： Compositions for the use of sewage or wastewater treatment, controlling odors or a combination thereof are disclosed, wherein the composition comprises at least one iron-based compound. Furthermore, methods of reducing the odors in a sewage or wastewater system are disclosed that include: adding a composition comprising at least one iron-based compound to a sewage or wastewater system. As used herein, the phrase “at least one iron-based compound” includes ferrous chloride, ferric chloride, ferrous sulfate, ferrate, polyferric sulfate, Ferix-3 (Fe2(SO4)3H2O) or a combination thereof.

摘要翻译： 公开了用于污水或废水处理，控制气味或其组合的组合物，其中所述组合物包含至少一种铁基化合物。 此外，公开了减少污水或废水系统中的气味的方法，其包括：向污水或废水系统中加入包含至少一种铁基化合物的组合物。 如本文所用，短语“至少一种铁基化合物”包括氯化亚铁，氯化铁，硫酸亚铁，高铁酸盐，聚硫酸铁，Ferix-3（Fe 2（SO 4）3 H 2 O）或其组合。