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    Methods for controlling microloading variation in semiconductor wafer layout and fabrication
    1.
    发明授权
    Methods for controlling microloading variation in semiconductor wafer layout and fabrication 有权
    用于控制半导体晶片布局和制造中的微加载变化的方法

    公开(公告)号：US09122832B2

    公开(公告)日：2015-09-01

    申请号：US12512932

    申请日：2009-07-30

    申请人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

    发明人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

    摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并且随后从晶片中移除留下期望的永久结构。

    Methods for defining and utilizing sub-resolution features in linear topology
    2.
    发明授权
    Methods for defining and utilizing sub-resolution features in linear topology 有权
    在线性拓扑中定义和利用子分辨率特征的方法

    公开(公告)号：US08225239B2

    公开(公告)日：2012-07-17

    申请号：US12479674

    申请日：2009-06-05

    申请人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks ,  Scott T. Becker

    发明人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks ,  Scott T. Becker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

    摘要翻译： 正常的布局形状根据虚拟炉排放置。 确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。 在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。 此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。 子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。

    Finfet transistor circuit
    4.
    发明授权
    Finfet transistor circuit 有权
    Finfet晶体管电路

    公开(公告)号：US08863063B2

    公开(公告)日：2014-10-14

    申请号：US13841951

    申请日：2013-03-15

    申请人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

    发明人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0886 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/02521 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/7853 ,  Y02P90/265

    摘要： A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.

    摘要翻译： 第一栅极级特征形成第一晶体管类型的第一鳍状晶体管和第二晶体管类型的第一鳍式晶体管的栅电极。 第二栅极级特征形成第一晶体管类型的第二鳍状晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二鳍状晶体管的栅电极。 第一和第二晶体管类型的第二finfet晶体管的栅电极彼此电连接。 第一和第二晶体管类型的第二finfet晶体管的栅电极位于栅极电极轨道的相对侧上，第一和第二晶体管类型的第一finfet晶体管的栅电极沿着栅电极轨道定位。

    Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
    5.
    发明授权
    Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos 有权
    具有根据制造保证光环定义和放置的动态阵列部分的半导体器件

    公开(公告)号：US08759882B2

    公开(公告)日：2014-06-24

    申请号：US13007582

    申请日：2011-01-14

    申请人： Scott T. Becker ,  Michael C. Smayling

    发明人： Scott T. Becker ,  Michael C. Smayling

    IPC分类号： H01L27/118

    CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11874 ,  H01L2027/11888 ,  Y02P90/265

    摘要： An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments.

    摘要翻译： 集成电路器件包括多个动态阵列部分，每个部分包括三个或更多个以其平行方式在其栅极电平内形成的线性导电部分，以沿第一方向纵向延伸。 相邻的一对动态阵列部分被定位成具有垂直于第一方向延伸的外周边界段的共同定位部分。 相邻的一对动态阵列部分的栅极电极层内的三个或更多个线性导电段中的一些在第一方向上共同对准并且由端对端间隔分开，该间隔跨越外周的共同定位部分 相邻的一对动态阵列部分的边界段。 这些端对端间隔中的每一个的尺寸被确定为确保第一相邻的一对动态阵列部分的每个栅电极级制造保证光晕部分没有共对齐的线性导电段。

    Finfet Transistor Circuit
    6.
    发明申请
    Finfet Transistor Circuit 有权
    Finfet晶体管电路

    公开(公告)号：US20130207199A1

    公开(公告)日：2013-08-15

    申请号：US13841951

    申请日：2013-03-15

    申请人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

    发明人： Scott T. Becker ,  Michael C. Smayling ,  Dhrumil Gandhi ,  Jim Mali ,  Carole Lambert ,  Jonathan R. Quandt ,  Daryl Fox

    IPC分类号： H01L27/088 ,  G06F17/50

    CPC分类号： H01L27/0886 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/02521 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/7853 ,  Y02P90/265

    摘要： A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.

    摘要翻译： 第一栅极级特征形成第一晶体管类型的第一鳍状晶体管和第二晶体管类型的第一鳍式晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二鳍状晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二鳍状晶体管的栅电极。 第一和第二晶体管类型的第二finfet晶体管的栅电极彼此电连接。 第一和第二晶体管类型的第二finfet晶体管的栅电极位于栅极电极轨道的相对侧上，第一和第二晶体管类型的第一finfet晶体管的栅电极沿着栅电极轨道定位。

    Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
    7.
    发明授权
    Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos 有权
    具有根据制造保证光环定义和放置的动态阵列部分的半导体器件

    公开(公告)号：US08283701B2

    公开(公告)日：2012-10-09

    申请号：US13007584

    申请日：2011-01-14

    申请人： Scott T. Becker ,  Michael C. Smayling

    发明人： Scott T. Becker ,  Michael C. Smayling

    IPC分类号： H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/74 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11874 ,  H01L2027/11888 ,  Y02P90/265

    摘要： An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending in the first direction. At least one of the linear conductive segments within the gate electrode level of a given dynamic array section is a non-gate linear conductive segment that does not form a gate electrode of a transistor. The non-gate linear conductive segment of either of the adjoining pair of dynamic array sections spans the co-located portion of outer peripheral boundary segment toward the other of the adjoining pair of dynamic array sections, and is contained within gate electrode level manufacturing assurance halo portions of the adjoining pair of dynamic array sections.

    摘要翻译： 集成电路器件包括多个动态阵列部分，每个部分包括三个或更多个以其平行方式在其栅极电平内形成的线性导电部分，以沿第一方向纵向延伸。 相邻的一对动态阵列部分被定位成具有在第一方向上延伸的外周边界段的共同定位部分。 给定动态阵列部分的栅极电平内的至少一个线性导电段是不形成晶体管的栅电极的非栅极线性导电段。 相邻的一对动态阵列部分中的任一个的非栅极线性导电部分跨越相邻的一对动态阵列部分中的另一个的外周边界段的共同定位部分，并且包含在栅电极级制造保证光晕 相邻的一对动态阵列部分的部分。