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    METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT
    4.
    发明申请
    METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT 有权
    SOI工艺电路替代服务模式的方法与装置

    公开(公告)号：US20120126871A1

    公开(公告)日：2012-05-24

    申请号：US12953593

    申请日：2010-11-24

    申请人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

    发明人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

    IPC分类号： G06F1/04

    CPC分类号： G06F1/324 ,  Y02D10/126

    摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

    摘要翻译： 一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。 基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。 通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

    Memory diagnostics system and method with hardware-based read/write patterns
    5.
    发明授权
    Memory diagnostics system and method with hardware-based read/write patterns 有权
    内存诊断系统和基于硬件读/写模式的方法

    公开(公告)号：US08607104B2

    公开(公告)日：2013-12-10

    申请号：US12972977

    申请日：2010-12-20

    申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

    发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

    IPC分类号： G06F11/00

    CPC分类号： G11C29/1201 ,  G11C29/022

    摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

    摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

    MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNS
    6.
    发明申请
    MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNS 有权
    存储器诊断系统和基于硬件的读/写模式的方法

    公开(公告)号：US20120159271A1

    公开(公告)日：2012-06-21

    申请号：US12972977

    申请日：2010-12-20

    申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

    发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

    IPC分类号： G06F11/263

    CPC分类号： G11C29/1201 ,  G11C29/022

    摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

    摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

    System to optimally order cycles originating from a single physical link
    7.
    发明授权
    System to optimally order cycles originating from a single physical link 失效

    公开(公告)号：US07111105B2

    公开(公告)日：2006-09-19

    申请号：US10038844

    申请日：2001-12-31

    申请人： Paras Shah ,  Ryan J. Hensley ,  Jaideep Dastidar

    发明人： Paras Shah ,  Ryan J. Hensley ,  Jaideep Dastidar

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4004

    摘要： A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

    Inter-queue ordering mechanism
    8.
    发明授权
    Inter-queue ordering mechanism 失效

    公开(公告)号：US07139859B2

    公开(公告)日：2006-11-21

    申请号：US10039130

    申请日：2001-12-31

    申请人： Jaideep Dastidar ,  Ryan J. Hensley ,  Michael Ruhovets ,  An H. Lam

    发明人： Jaideep Dastidar ,  Ryan J. Hensley ,  Michael Ruhovets ,  An H. Lam

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4059

    摘要： A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

    APPARATUS AND METHOD FOR SERVICING LATENCY-SENSITIVE MEMORY REQUESTS
    9.
    发明申请
    APPARATUS AND METHOD FOR SERVICING LATENCY-SENSITIVE MEMORY REQUESTS 审中-公开
    用于维护敏感记忆体要求的装置和方法

    公开(公告)号：US20130124805A1

    公开(公告)日：2013-05-16

    申请号：US13293791

    申请日：2011-11-10

    申请人： Todd M. Rafacz ,  Kevin M. Lepak ,  Ryan J. Hensley

    发明人： Todd M. Rafacz ,  Kevin M. Lepak ,  Ryan J. Hensley

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642 ,  G06F13/1626

    摘要： A shared memory controller and method of operation are provided. The shared memory controller is configured for use with a plurality of processors such as a central processing unit or a graphics processing unit. The shared memory controller includes a command queue configured to hold a plurality of memory commands from the plurality of processors, each memory command having associated priority information. The shared memory controller includes boost logic configured to identify a latency sensitive memory command and update the priority information associated with the memory command to identify the memory command as latency sensitive. The boost logic may be configured to identify a latency sensitive processor command. The boost logic may be configured to track time duration between successive latency sensitive memory commands.

    摘要翻译： 提供共享存储器控制器和操作方法。 共享存储器控制器被配置为与诸如中央处理单元或图形处理单元的多个处理器一起使用。 共享存储器控制器包括配置为保存来自多个处理器的多个存储器命令的命令队列，每个存储器命令具有相关联的优先级信息。 共享存储器控制器包括被配置为识别延迟敏感存储器命令并且更新与存储器命令相关联的优先级信息的升压逻辑，以将存储器命令标识为延迟敏感。 升压逻辑可以被配置为识别等待时间敏感的处理器命令。 升压逻辑可以被配置为跟踪连续的延迟敏感存储器命令之间的持续时间。

    Method and apparatus for a dual mode PCI/PCI-X device
    10.
    发明授权
    Method and apparatus for a dual mode PCI/PCI-X device 失效
    双模式PCI / PCI-X设备的方法和装置

    公开(公告)号：US06950897B2

    公开(公告)日：2005-09-27

    申请号：US09792833

    申请日：2001-02-23

    申请人： Ryan J. Hensley ,  Jaideep Dastidar ,  Timothy K. Waldrop

    发明人： Ryan J. Hensley ,  Jaideep Dastidar ,  Timothy K. Waldrop

    IPC分类号： G06F13/10 ,  G06F13/36 ,  G06F13/40 ,  G06F13/92

    CPC分类号： G06F13/4004

    摘要： A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

    摘要翻译： 公开了一种用于促进计算机系统中的数据处理的技术。 该技术利用逻辑来实现PCI / PCI-X计算机系统的双模式设计，无论系统运行哪种模式，都能实现最佳效率。该技术涉及实现两组发送和接收元件，一种调谐到 PCI协议定时，另一个到PCI-X协议。 因此，允许系统处理PCI和PCI-X交易，而不会对其他功能模式产生不利影响。 该技术还使操作员可以分别调整每个协议的时钟定时，而不会对其他操作协议产生不利影响。