公开(公告)号：US08373447B2

公开(公告)日：2013-02-12

申请号：US12953593

申请日：2010-11-24

申请人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

发明人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

IPC分类号： H03K17/00 ,  G06F1/08

CPC分类号： G06F1/324 ,  Y02D10/126

摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

摘要翻译： 一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。 基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。 通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

公开(公告)号：US20120126871A1

公开(公告)日：2012-05-24

申请号：US12953593

申请日：2010-11-24

申请人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

发明人： Joseph E. Kidd ,  Brian W. Amick ,  Ryan J. Hensley ,  James R. Magro ,  Ronald L. Pettyjohn

IPC分类号： G06F1/04

CPC分类号： G06F1/324 ,  Y02D10/126

摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

摘要翻译： 一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。 基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。 通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

公开(公告)号：US06889334B1

公开(公告)日：2005-05-03

申请号：US09969300

申请日：2001-10-02

申请人： James R. Magro ,  Bruce A. Loyer ,  Pratik M. Mehta

发明人： James R. Magro ,  Bruce A. Loyer ,  Pratik M. Mehta

IPC分类号： G06F1/06 ,  G11C7/10 ,  H04L7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2254 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037

摘要： A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

摘要翻译： 用于将数据选通的定时与存储器模块提供的数据协调到存储器控制器的系统，读取基于处理器的系统的数据FIFO，从而提供多种校准模式。 校准PDL（可编程延迟线）用于重复测试测试数据选通遍历存储器控制器电路的一部分所花费的时间，并且基于所花费的时间生成校准值。 校准过程可以以几种模式中的任何一种启动，包括：根据预定的时间表; 以软件实现 响应于在一个或多个位置处采样的环境因素如温度或电压的变化; 响应软件驱动的触发器; 或者响应于用户发起的触发，通过经由用户接口输入到基于处理器的系统或通过软件命令传送到本发明的系统。

公开(公告)号：US06556952B1

公开(公告)日：2003-04-29

申请号：US09564208

申请日：2000-05-04

申请人： James R. Magro

发明人： James R. Magro

IPC分类号： G06F1130

CPC分类号： G06F11/3409 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： An integrated circuit, system and method monitors parameter performance for optimization of controller performance. The integrated circuit includes a memory controller, one or more buffers coupled to the memory controller, and a performance monitoring circuit coupled to the one or more buffers and an SDRAM controller, the performance monitoring circuit to receive at least one parameter related to the buffers and provide statistical data related to the parameter. The statistical data may be used to set an amount of data to accumulate in the one or more buffers. A method includes transmitting one or more parameters related to performance of one more components of an integrated circuit to a performance monitoring circuit located within the integrated circuit. The performance monitoring circuit then determines statistical data related to the parameter independent of an interrupt to the integrated circuit. Further, the method includes transmitting the statistical data to a register in the integrated circuit and software interpreting the statistical data according to predetermined parameters to improve functionality of the component. The method includes either altering functionality or maintaining functionality of the component of the integrated circuit according to the interpretation of the statistical data.

摘要翻译： 集成电路，系统和方法监控参数性能，以优化控制器性能。 集成电路包括存储器控制器，耦合到存储器控制器的一个或多个缓冲器以及耦合到所述一个或多个缓冲器和SDRAM控制器的性能监视电路，所述性能监视电路接收与所述缓冲器有关的至少一个参数，以及 提供与参数相关的统计数据。 统计数据可以用于设置在一个或多个缓冲器中累积的数据量。 一种方法包括将与集成电路的多个组件的性能相关的一个或多个参数发送到位于集成电路内的性能监视电路。 然后，性能监视电路确定与参数无关的统计数据，与集成电路的中断无关。 此外，该方法包括将统计数据发送到集成电路中的寄存器和根据预定参数解释统计数据的软件以改善组件的功能。 该方法包括根据统计数据的解释来改变功能或维护集成电路的组件的功能。

公开(公告)号：US06976204B1

公开(公告)日：2005-12-13

申请号：US09882417

申请日：2001-06-15

申请人： Eric G. Chambers ,  James R. Magro ,  Dan S. Mudgett

发明人： Eric G. Chambers ,  James R. Magro ,  Dan S. Mudgett

IPC分类号： G11C7/10 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C7/1039 ,  G06F11/106 ,  G11C7/1006

摘要： A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.

摘要翻译： 一种用于校正用于流水线读取的存储器中的错误数据的电路和方法。 存储器控制器包括控制单元，存储单元和错误检测和校正单元。 控制单元被配置为响应于存储器读取请求从存储器子系统读取包括相关联的纠错码的数据。 错误检测和校正单元被耦合以接收数据并被配置为基于相关联的纠错码来确定该数据中是否存在错误。 控制单元被配置为在存储单元中存储与存储器读取请求相对应的数据是错误的指示。 控制单元还被配置为检测存储单元中的指示并且响应地执行来自存储器子系统的数据的后续读取并将该数据的校正版本写回到存储器子系统。

公开(公告)号：US06681301B1

公开(公告)日：2004-01-20

申请号：US09969303

申请日：2001-10-02

申请人： Pratik M. Mehta ,  James R. Magro

发明人： Pratik M. Mehta ,  James R. Magro

IPC分类号： G06F1200

CPC分类号： G06F13/1694

摘要： A system that enables a memory controller to control data transfers with memory modules, such as DIMMs (double in-line memory modules), of either a “by 4” (×4) type or a non-by-4 type (non-×4). Both ×4 and non-×4 DIMMs may be used in the system simultaneously, and the memory controller dynamically adjusts its enable and other signals as needed. Data strobe signals are provided to and from DIMMs over a data strobe transfer circuits which in the case of a non-×4 DIMM handles data strobes for an entire byte of data, while in the case of ×4 DIMM the data transfer circuit handles data strobes for one nibble (four bits) of a byte of data. A hybrid data mask/data strobe transfer circuit handles the other nibble of a byte of data in the case of data transfers for ×4 DIMMs, and handles data mask signals for write operations for non-×4 DIMMs.

摘要翻译： 一种使内存控制器可以使用“by 4”（x4）类型或非4类（非x4）类型的内存模块（例如DIMM（双列直插式内存模块））控制数据传输的系统 ）。 x4和non-x4 DIMM都可以同时在系统中使用，并且存储器控制器根据需要动态调整其使能和其他信号。 数据选通信号通过数据选通传输电路提供给DIMM，数据选通传输电路在非x4 DIMM的情况下处理整个数据字节的数据选通，而在x4 DIMM的情况下，数据传输电路处理数据选通 一个字节数据的一个四位（四位）。 混合数据掩码/数据选通传输电路在x4 DIMM的数据传输的情况下处理一字节数据的另一半字节，并处理用于非x4 DIMM的写入操作的数据掩码信号。

公开(公告)号：US06721816B1

公开(公告)日：2004-04-13

申请号：US10083874

申请日：2002-02-27

申请人： James R. Magro ,  Stephen C. Ennis

发明人： James R. Magro ,  Stephen C. Ennis

IPC分类号： G06F1314

CPC分类号： G06F13/20

摘要： An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

摘要翻译： 计算机系统的输入/输出节点的仲裁机制。 仲裁机制包括用于存储与发布的虚拟通道和第二虚拟通道相对应的接收的控制命令的缓冲电路。 每个控制命令包括指示控制命令的源的标识符值。 标签电路，其可以在存储控制命令之前生成每个控制命令的标签值。 标签值可以指示相对于其他控制命令接收每个控制命令的顺序，并且可以取决于标识符值。 此外，仲裁电路可以根据每个控制命令的标签值来仲裁存储在缓冲器电路内的控制命令。 仲裁电路可以独立于标签值选择给定的控制命令并且具有设置的标志位。

公开(公告)号：US06516362B1

公开(公告)日：2003-02-04

申请号：US09379014

申请日：1999-08-23

申请人： James R. Magro ,  Michael S. Quimby

发明人： James R. Magro ,  Michael S. Quimby

IPC分类号： G06F1300

CPC分类号： G06F5/06 ,  G06F13/1689 ,  G06F13/4059 ,  G06F13/4217

摘要： A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock. The return register presents the return data at the next read cycle according to the slower clock signal.

摘要翻译： 基于处理器的系统利用时钟同步来提供以不同频率工作的多个计算机设备之间的通信。 在运行不同频率的时钟信号之间维持相位关系，使得当时钟信号同相时以更快的频率工作的设备的读取周期被启动。 当时钟信号异相时，启动较快频率器件的写周期。 通过将时钟信号一起采样来指示相位关系来产生同步信号。 另外，从更快的时钟导出的返回时钟驱动外部设备。 从内部设备发送到外部设备的信息通过由返回时钟驱动的寄存器。 由于寄存器根据返回时钟发送所有信息，因此避免了向外部设备提供的信息的定时延迟。 返回数据也根据返回时钟计时回到寄存器中。 返回寄存器根据较慢的时钟信号在下一个读取周期呈现返回数据。

公开(公告)号：US06260081B1

公开(公告)日：2001-07-10

申请号：US09198797

申请日：1998-11-24

申请人： James R. Magro ,  Daniel P. Mann ,  Floyd Goodrich, III

发明人： James R. Magro ,  Daniel P. Mann ,  Floyd Goodrich, III

IPC分类号： G06F300

CPC分类号： G06F13/28

摘要： A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.

摘要翻译： 直接内存访问引擎支持多个虚拟直接内存访问通道。 直接存储器访问引擎包括直接存储器访问控制器和存储器中的参数表，其包含用于多个虚拟直接存储器访问通道的参数。 控制器引擎提供单个物理直接存储器访问通道和多个虚拟直接存储器访问通道。 多个虚拟直接存储器访问通道中的一个直接存储器访问通道可以在给定时间处于活动状态。 活动通道的参数可以从参数表加载到直接存储器访问控制器的物理直接存储器访问控制块和物理直接存储器访问信道资源。 直接存储器访问控制器的物理直接存储器访问控制块利用物理直接存储器访问信道资源，以基于所加载的参数为活动信道执行直接存储器访问传输。 物理直接存储器访问信道资源由多个虚拟直接存储器访问信道共享。 直接存储器访问引擎还包括用于多个虚拟直接存储器访问信道中的活动信道的直接存储器访问请求线和直接存储器访问确认线。

公开(公告)号：US06754779B1

公开(公告)日：2004-06-22

申请号：US09378870

申请日：1999-08-23

申请人： James R. Magro

发明人： James R. Magro

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F2212/6022

摘要： Improved performance for data read operation is achieved in a read buffer that receives and stores requested information in response to read requests from multiple requesting master devices. A full cache line of data is read from the memory device into the read buffer in response to any read request. The requested data and any additional data within the retrieved cache line is available to any requesting master device in zero wait states. In addition, a next cache line of data is retrieved concurrently while the previously stored data is provided to the requesting master pursuant to the original read request. Subsequent read requests that matches any data stored in the read buffer is provided pursuant to a subsequent read request in zero wait states.

摘要翻译： 在读取缓冲器中实现了数据读取操作的改善，该读取缓冲器响应于来自多个请求主设备的读取请求而接收并存储所请求的信息。 响应于任何读取请求，将完整高速缓存行数据从存储器件读取到读取缓冲器中。 所请求的数据和检索到的高速缓存行中的任何附加数据对零等待状态的任何请求主设备都是可用的。 此外，同时检索下一个高速缓存行数据，同时根据原始读取请求将先前存储的数据提供给请求主机。 随后的读取请求与存储在读取缓冲器中的任何数据相匹配，依照随后的零等待状态的读取请求来提供。