公开(公告)号：US08822286B2

公开(公告)日：2014-09-02

申请号：US14050748

申请日：2013-10-10

Applicant: Broadcom Corporation

Inventor： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract translation: 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20140038404A1

公开(公告)日：2014-02-06

申请号：US14050748

申请日：2013-10-10

Applicant: Broadcom Corporation

Inventor： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Abstract translation: 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20160308042A1

公开(公告)日：2016-10-20

申请号：US15193718

申请日：2016-06-27

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Frank Hui

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。

公开(公告)号：US09406793B2

公开(公告)日：2016-08-02

申请号：US14529959

申请日：2014-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Frank Hui

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。

公开(公告)号：US20160005850A1

公开(公告)日：2016-01-07

申请号：US14529959

申请日：2014-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Frank Hui

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。