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    Semiconductor Device with a Vertical Channel Formed Through a Plurality of Semiconductor Layers
    4.
    发明申请
    Semiconductor Device with a Vertical Channel Formed Through a Plurality of Semiconductor Layers 有权
    具有通过多个半导体层形成的垂直通道的半导体器件

    公开(公告)号：US20160308042A1

    公开(公告)日：2016-10-20

    申请号：US15193718

    申请日：2016-06-27

    Applicant: Broadcom Corporation

    Inventor： Sam Ziqun ZHAO ,  Frank Hui

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

    CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

    Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

    Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。

    SEMICONDUCTOR DEVICE WITH A VERTICAL CHANNEL
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH A VERTICAL CHANNEL 有权
    具有垂直通道的半导体器件

    公开(公告)号：US20160005850A1

    公开(公告)日：2016-01-07

    申请号：US14529959

    申请日：2014-10-31

    Applicant: Broadcom Corporation

    Inventor： Sam Ziqun ZHAO ,  Frank Hui

    IPC: H01L29/78 ,  H01L29/10

    CPC classification number: H01L29/7809 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/781 ,  H01L29/7827

    Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

    Abstract translation: 半导体器件和制造方法被提供用于使通道和栅极长度独立于光刻。 此外，提供半导体器件和制造方法用于增加漏极和沟道之间的电阻率，以允许更高的电压操作。 例如，半导体器件包括注入形成源极或漏极之一的半导体衬底中的第一掺杂层和设置在第一掺杂层上的栅极金属层。 半导体器件还包括设置在形成另一个源极或漏极的栅极金属上的第二掺杂层，其中第一掺杂层，栅极金属层和第二掺杂层形成半导体器件的垂直堆叠层。 所述半导体器件还包括形成在沟槽中的导电沟道，所述沟槽垂直延伸穿过所述垂直堆叠层并终止于所述半导体衬底。

    Identifying Defective Components on a Wafer Using Component Triangulation
    8.
    发明申请
    Identifying Defective Components on a Wafer Using Component Triangulation 有权
    使用组件三角测量识别晶圆上的有缺陷的组件

    公开(公告)号：US20130311127A1

    公开(公告)日：2013-11-21

    申请号：US13944430

    申请日：2013-07-17

    Applicant: Broadcom Corporation

    Inventor： Arya Reza BEHZAD ,  Ahmadreza ROFOUGARAN ,  Sam Ziqun ZHAO ,  Jesus Alfonso CASTANEDA ,  Michael BOERS

    IPC: G01R31/319

    CPC classification number: G01R31/319 ,  G01R31/2834 ,  G01R31/3025 ,  G01R31/311 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2924/0002 ,  Y10T29/49121 ,  H01L2924/00

    Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

    Abstract translation: 公开了同时无线地测试形成在半导体晶片上的半导体元件的方法和装置。 半导体部件通过公共通信信道将各自的测试结果传送到无线自动测试设备。 多个接收天线在三维空间中观察多个方向的结果。 无线自动测试设备确定一个或多个半导体组件是否按预期运行，并且可选地，可以使用三维空间的属性来确定一个或多个半导体组件的位置。 无线测试设备还可以通过检测在独立测试操作之前，期间和/或之后由半导体晶片发射，传输和/或反射的红外能量来确定半导体组件的性能。

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