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公开(公告)号:US09111369B2
公开(公告)日:2015-08-18
申请号:US13782081
申请日:2013-03-01
申请人: Broadcom Corporation
发明人: Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiadong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号: G06T1/60 , G06T1/20 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号: G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要: Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.
摘要翻译: 这里公开了图形加速器的各种实施例,其可以包括集成电路。 集成电路可以包括本地存储器; 直接存储器访问(DMA)引擎; 处理器 和一个或多个处理管道。 本地存储器存储包括多个像素的图形数据。 DMA引擎在本地存储器和外部存储器之间传输图形数据。 处理器并行地执行至少一部分像素的组件上的至少一个操作。 一个或多个处理管线处理图形数据。 图形加速器对操作数起作用,并产生一组像素的输出,而DMA引擎为未来的像素运算组提供操作数,并通过将数据指向一个或多个处理流水线将数据从外部存储器传输到一个或多个处理流水线 或更多管道。
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公开(公告)号:US20150317085A1
公开(公告)日:2015-11-05
申请号:US14790923
申请日:2015-07-02
申请人: Broadcom Corporation
发明人: Alexander G. MacInnis , Chengfuh Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
CPC分类号: G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译: 在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。 图形显示系统处理模拟视频输入,数字视频输入和图形输入。 该系统包含由图形系统,CPU和其他外围设备共享的统一存储器架构。 统一存储器架构使用实时调度来服务任务。 关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划,同时根据需要为非实时任务进行服务。
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公开(公告)号:US09575665B2
公开(公告)日:2017-02-21
申请号:US14790923
申请日:2015-07-02
申请人: Broadcom Corporation
发明人: Alexander G. MacInnis , Chengfuh Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号: G06F3/00 , G06F3/06 , G06T1/60 , G06T1/20 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号: G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译: 在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。 图形显示系统处理模拟视频输入,数字视频输入和图形输入。 该系统包含由图形系统,CPU和其他外围设备共享的统一存储器架构。 统一存储器架构使用实时调度来服务任务。 关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划,同时根据需要为非实时任务进行服务。
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公开(公告)号:US20140078155A1
公开(公告)日:2014-03-20
申请号:US13782081
申请日:2013-03-01
申请人: Broadcom Corporation
发明人: Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiadong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号: G06T1/20
CPC分类号: G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要: Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.
摘要翻译: 这里公开了图形加速器的各种实施例,其可以包括集成电路。 集成电路可以包括本地存储器; 直接存储器访问(DMA)引擎; 处理器 和一个或多个处理管道。 本地存储器存储包括多个像素的图形数据。 DMA引擎在本地存储器和外部存储器之间传输图形数据。 处理器并行地执行至少一部分像素的组件上的至少一个操作。 一个或多个处理管线处理图形数据。 图形加速器对操作数起作用,并产生一组像素的输出,而DMA引擎为未来的像素运算组提供操作数,并通过将数据指向一个或多个处理流水线将数据从外部存储器传输到一个或多个处理流水线 或更多管道。
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