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    Variable gain amplifier for low voltage applications
    1.
    发明申请
    Variable gain amplifier for low voltage applications 有权
    用于低电压应用的可变增益放大器

    公开(公告)号：US20040219898A1

    公开(公告)日：2004-11-04

    申请号：US10747124

    申请日：2003-12-30

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Rudy Van De Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

    IPC: H04B007/00

    CPC classification number: H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

    Abstract translation: 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。

    Offset compensated comparing amplifier
    2.
    发明申请
    Offset compensated comparing amplifier 有权

    公开(公告)号：US20030001768A1

    公开(公告)日：2003-01-02

    申请号：US10079814

    申请日：2002-02-22

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult

    IPC: H03M001/34

    CPC classification number: H03F3/70 ,  H03M1/361

    Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.

    Digital to analog converter with reduced ringing
    3.
    发明申请
    Digital to analog converter with reduced ringing 失效

    公开(公告)号：US20040227653A1

    公开(公告)日：2004-11-18

    申请号：US10810053

    申请日：2004-03-26

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M001/66

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Analog to digital converter
    4.
    发明申请
    Analog to digital converter 失效
    模数转换器

    公开(公告)号：US20040113827A1

    公开(公告)日：2004-06-17

    申请号：US10688122

    申请日：2003-10-17

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Aaron W. Buchwald

    IPC: H03M001/34

    CPC classification number: H03M1/0646 ,  H03M1/36

    Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

    Abstract translation: 提供了一种用于减少模数转换器中连续的单元对的输出之间的失配的电路。电压输入装置耦合到每个单元的第一输入端以引入输入电压。 参考电压装置耦合到每个单元的第二输入端子以引入参考电压的渐进分数。 低阻抗装置耦合在相应的第一输出端子之间，并连接在连续的电池中的相应的第二输出端子之间，以将负载电流牵引到连续的电池，影响相对电压，从而减少电池错配对这些输出端子的影响。 最后，高阻抗装置耦合到连续单元中的每个第一输出端和每个第二输出端。

    Capacitive folding circuit for use in a folding/interpolating analog-to-digital converter
    6.
    发明申请
    Capacitive folding circuit for use in a folding/interpolating analog-to-digital converter 失效
    用于折叠/内插模数转换器的电容折叠电路

    公开(公告)号：US20020196172A1

    公开(公告)日：2002-12-26

    申请号：US10071252

    申请日：2002-02-11

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult

    IPC: H03M001/34

    CPC classification number: H03M1/205 ,  H03M1/141

    Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

    Abstract translation: 一种M位折叠/内插模数转换器（ADC）电路，包括参考电压发生器，转换器，内插器，放大级，比较器和编码器。 转换器具有放大器，其接收多个第一参考电压信号中的至少一个并输出多个粗位。 转换器还具有N个折叠块，其输出多个折叠信号。 每个折叠块包括多个电容器，差分放大器和反馈元件。 然后，由转换器输出的折叠信号被内插，放大，比较和输出为多个精细位。 编码器接收粗细位并输出数字信号。

    High speed latch comparators
    7.
    发明申请
    High speed latch comparators 有权
    高速锁存比较器

    公开(公告)号：US20040041611A1

    公开(公告)日：2004-03-04

    申请号：US10649808

    申请日：2003-08-28

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

    IPC: H03K003/037

    CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

    Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

    Digital to analog converter with reduced ringing
    9.
    发明申请
    Digital to analog converter with reduced ringing 有权

    公开(公告)号：US20030085829A1

    公开(公告)日：2003-05-08

    申请号：US10320016

    申请日：2002-12-16

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M001/66

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

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