-
公开(公告)号：US08971832B2
公开(公告)日：2015-03-03
申请号：US13909819
申请日：2013-06-04
Applicant: Broadcom Corporation
Inventor： Klaas Bult , Rudy Van De Plassche , Pieter Vorenkamp , Arnoldus Venes
CPC classification number: H03G3/30 , H03F1/34 , H03F3/195 , H03F3/24 , H03F3/45188 , H03F3/45192 , H03F2200/294 , H03F2200/331 , H03F2200/372 , H03F2200/513 , H03F2203/45644 , H03G1/0029 , H04B2001/0433
Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
Abstract translation: 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。
-
公开(公告)号：US09853615B2
公开(公告)日：2017-12-26
申请号：US15139030
申请日：2016-04-26
Applicant: BROADCOM CORPORATION
Inventor： Md Shakil Akter , Klaas Bult
CPC classification number: H03F3/45179 , H03F1/3211 , H03F1/34 , H03F3/45 , H03F3/45071 , H03F3/45085 , H03F3/45183 , H03F2200/294 , H03F2200/297 , H03F2200/372 , H03F2200/489 , H03G1/0029 , H03G1/0052 , H03G3/3015 , H03M1/0695 , H03M1/124 , H03M1/164
Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).
-
3.发明申请公开(公告)号：US20140167989A1
公开(公告)日：2014-06-19
申请号：US13720691
申请日：2012-12-19
Applicant: BROADCOM CORPORATION
Inventor： Frank van der GOES , Christopher Ward , Klaas Bult
IPC: H03M1/06
CPC classification number: H03M1/06 , H03M1/1057 , H03M1/1215
Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
Abstract translation: 公开了一种多通道模数转换器（ADC），其能够补偿其一个或多个损伤，使得其数字输出准确地表示其模拟输入。 多通道ADC可以补偿多通道ADC使用的采样时钟的多个相位之间的不需要的相位偏移，多通道ADC中的通道之间的不需要的带宽不匹配和/或多通道ADC中的通道之间的不期望的增益失配 -lane ADC提供一些例子。
-
Patent Agency Ranking
公开(公告)号：US20170302237A1
公开(公告)日：2017-10-19
申请号：US15139030
申请日：2016-04-26
Applicant: BROADCOM CORPORATION
Inventor： Md Shakil Akter , Klaas Bult
CPC classification number: H03F3/45179 , H03F1/3211 , H03F1/34 , H03F3/45 , H03F3/45071 , H03F3/45085 , H03F3/45183 , H03F2200/294 , H03F2200/297 , H03F2200/372 , H03F2200/489 , H03G1/0029 , H03G1/0052 , H03G3/3015 , H03M1/0695 , H03M1/124 , H03M1/164
Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).
-
公开(公告)号：US20160254820A1
公开(公告)日：2016-09-01
申请号：US14706543
申请日：2015-05-07
Applicant: Broadcom Corporation
Inventor： Christopher WARD , Klaas Bult , Iniyavan Elumalai
CPC classification number: H03M1/0604 , H03M1/742
Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.
Abstract translation: 半导体器件制造操作通常用于在半导体衬底上制造一个或多个集成电路。 半导体器件制造操作在制造层的布置上形成一个或多个晶体管，以形成将不常用的电容（通常被称为寄生电容）引入到一个或多个晶体管中的一个或多个集成电路。 一个或多个集成电路包括一个或多个补偿模块，当与一个或多个晶体管的寄生电容组合时，理想地线性化由一个或多个晶体管的寄生电容引起的非线性。 例如，一个或多个补偿模块包含与一个或多个晶体管的寄生电容成反比关系的非线性或分段线性传递函数。
-
公开(公告)号：US09432038B1
公开(公告)日：2016-08-30
申请号：US14706543
申请日：2015-05-07
Applicant: Broadcom Corporation
Inventor： Christopher Ward , Klaas Bult , Iniyavan Elumalai
CPC classification number: H03M1/0604 , H03M1/742
Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.
Abstract translation: 半导体器件制造操作通常用于在半导体衬底上制造一个或多个集成电路。 半导体器件制造操作在制造层的布置上形成一个或多个晶体管，以形成将不常用的电容（通常被称为寄生电容）引入到一个或多个晶体管中的一个或多个集成电路。 一个或多个集成电路包括一个或多个补偿模块，当与一个或多个晶体管的寄生电容组合时，理想地线性化由一个或多个晶体管的寄生电容引起的非线性。 例如，一个或多个补偿模块包含与一个或多个晶体管的寄生电容成反比关系的非线性或分段线性传递函数。
-
7.发明授权公开(公告)号：US08749410B1
公开(公告)日：2014-06-10
申请号：US13720691
申请日：2012-12-19
Applicant: Broadcom Corporation
Inventor： Frank Van Der Goes , Christopher Ward , Klaas Bult
IPC: H03M1/06
CPC classification number: H03M1/06 , H03M1/1057 , H03M1/1215
Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
Abstract translation: 公开了一种多通道模数转换器（ADC），其能够补偿其一个或多个损伤，使得其数字输出准确地表示其模拟输入。 多通道ADC可以补偿多通道ADC使用的采样时钟的多个相位之间的不需要的相位偏移，多通道ADC中的通道之间的不需要的带宽不匹配和/或多通道ADC中的通道之间的不期望的增益失配 -lane ADC提供一些例子。
-
公开(公告)号：US20140002194A1
公开(公告)日：2014-01-02
申请号：US13909819
申请日：2013-06-04
Applicant: Broadcom Corporation
Inventor： Klaas Bult , Rudy Van de Plassche , Pieter Vorenkamp , Arnoldus Venes
IPC: H03G3/30
CPC classification number: H03G3/30 , H03F1/34 , H03F3/195 , H03F3/24 , H03F3/45188 , H03F3/45192 , H03F2200/294 , H03F2200/331 , H03F2200/372 , H03F2200/513 , H03F2203/45644 , H03G1/0029 , H04B2001/0433
Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
Abstract translation: 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.023 seconds)
