-
公开(公告)号：US06931343B2
公开(公告)日：2005-08-16
申请号：US10666410
申请日：2003-09-19
CPC分类号： H04L27/364 , H03C3/406 , H03D3/008 , H03D3/009 , H04B17/14
摘要： An on-signal calibration system I and Q signals of a transmitter to remove distortions in the RF output signal. The transmitter generates I and Q values and converts, modulates and combines the I and Q values into the RF output signal for transmission. The calibration system includes a detector, a sampler, a selector, an imbalance estimator, and an IQ corrector. The detector senses the RF output signal and provides a detection signal indicative thereof. The sampler samples the detection signal and provides digital samples. The selector selects from among the digital samples that correspond to predetermined ranges of the I and Q values, or otherwise predetermined selection boxes at predetermined phases. The imbalance estimator determines at least one imbalance estimate based on selected digital samples. The IQ corrector corrects the I and Q values using at least one imbalance estimate.
摘要翻译： 发射机的信号校准系统I和Q信号，以消除RF输出信号中的失真。 发射机产生I和Q值，并将I和Q值转换，调制和组合成RF输出信号进行传输。 校准系统包括检测器，采样器，选择器，不平衡估计器和IQ校正器。 检测器感测RF输出信号并提供指示其的检测信号。 采样器对检测信号进行采样，并提供数字采样。 选择器从数字样本中选择对应于I和Q值的预定范围，或者在预定阶段选择预定的选择框。 不平衡估计器基于所选择的数字样本确定至少一个不平衡估计。 IQ校正器使用至少一个不平衡估计来校正I和Q值。
-
公开(公告)号：US07173988B2
公开(公告)日：2007-02-06
申请号：US10338362
申请日：2003-01-08
CPC分类号： H04L27/0014 , H04L2027/0046
摘要： A method of canceling gain and phase imbalance including estimating a cancellation parameter based on the signal divided by its complex conjugate, calculating a correction value for the signal using the cancellation parameter, and correcting the signal by subtracting the correction value from the signal. Estimate the cancellation parameter may include performing a stochastic gradient algorithm or a least squares estimate. A cancellation system including a conjugate conversion unit, an estimator, a combiner, a converter, and a subtractor. The estimator estimates a cancellation parameter and the combiner combines the cancellation parameter and the complex conjugate signal to provide a cancellation signal. The converter converts the cancellation signal to a correction signal, and the subtractor subtracts the correction signal from the imbalanced signal to provide a corrected signal. The combiner may be an adaptable tap of a digital signal processing circuit.
摘要翻译： 一种消除增益和相位不平衡的方法，包括基于由其复共轭除以的信号来估计消除参数，使用消除参数计算信号的校正值，以及通过从该信号中减去校正值来校正信号。 估计取消参数可以包括执行随机梯度算法或最小二乘估计。 包括共轭转换单元，估计器，组合器，转换器和减法器的抵消系统。 估计器估计消除参数，并且组合器组合消除参数和复共轭信号以提供消除信号。 转换器将消除信号转换为校正信号，减法器从不平衡信号中减去校正信号以提供校正信号。 组合器可以是数字信号处理电路的适配抽头。
-
3.发明授权Digital communications modulator having a modulation processor which supports high data rates 失效具有支持高数据速率的调制处理器的数字通信调制器公开(公告)号：US06337606B1
公开(公告)日：2002-01-08
申请号：US09241697
申请日：1999-02-02
IPC分类号： H04L2720
CPC分类号： H04L25/03834 , H04L27/2071
摘要： An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
摘要翻译： IC调制处理器（28）可以被配置为以单芯片模式操作以适应处理器（28）的最大时钟速率的波特率，并且以双芯片模式适应超过最大时钟速率的波特率 。 IC调制处理器（28）对传送输入数据流（22）的通信信号执行数字处理。 在相位映射器（50）之后提供脉冲整形滤波器（54-57）。 脉冲整形滤波器（54-57）被实现为一对半滤波器。 在双芯片模式下，脉冲整形分布在两个IC调制处理器（28）之间。 内插器（86）和线性化器（106）跟随脉冲整形滤波器（54-57）。
-
公开(公告)号：US5671257A
公开(公告)日：1997-09-23
申请号：US468921
申请日：1995-06-06
CPC分类号： H04L7/0054 , H03L7/087 , H04L7/0334 , H03L7/091 , H04L7/0083
摘要： A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.
摘要翻译： 数字通信接收机（10）每个符号采用基带模拟信号（12）的一个复样本（20）。 矩形到极化转换器（26）将复数样本的相位属性与幅度属性分开。 相位处理器（28）识别在相邻符号之间发生相对大的相位变化时发生的时钟调整机会。 幅度处理器（32）仅在时钟调整机会期间影响符号定时。 当在时钟调整机会期间检测到减小的幅度变化时，幅度处理器（32）在锁相环中提前符号定时，并且在时钟调整机会期间检测到增加幅度变化时延迟符号定时。 可以使用内插器（66）来估计样本之间的幅度值，使得在采样的幅度值和估计的幅度值之间确定幅度变化。
-
5.发明授权Method for baud-clock phase synchronization in a TDMA digital communications system and apparatus therefor 失效TDMA数字通信系统中波特率相位同步的方法及其装置公开(公告)号：US06452948B1
公开(公告)日：2002-09-17
申请号：US09095116
申请日：1998-06-10
IPC分类号： H04B138
CPC分类号： H04W56/0035 , H04B7/2681 , H04L7/0029 , H04L7/0091
摘要： A time division multiple access digital communications system (12) is provided. The system (12) has a base station (14) configured to generate a receive baud clock (86) and has a receiver (18) and a transmitter (20). The system also has a subscriber unit (16) configured to generate a transmit baud clock (50), and has a transmitter (28) and a receiver (26). The subscriber unit transmitter (28) is configured to transmit a reverse channel signal (54) that incorporates the transmit baud clock (50) as a component thereof. The base station receiver (18) is configured to receive the reverse channel signal (54) from the subscriber unit (16) and produce a phase-error signal (&mgr;′) in response to a phase difference between the transmit baud clock (50) and the receive baud clock (86). The base station transmitter (20) is configured to transmit the phase-error signal (&mgr;′) to the subscriber unit receiver (26). The subscriber unit transmitter (28) contains an interpolator (122) configured to adjust the phase of the transmit baud clock (50) in response to the phase-error signal.
摘要翻译： 提供了一种时分多址数字通信系统（12）。 系统（12）具有被配置为产生接收波特率时钟（86）并具有接收机（18）和发射机（20）的基站（14）。 该系统还具有用于生成发射波特率时钟（50）的用户单元（16），并且具有发射机（28）和接收机（26）。 用户单元发射机（28）被配置为发送包含发射波特率时钟（50）作为其组成部分的反向信道信号（54）。 基站接收器（18）被配置为从用户单元（16）接收反向信道信号（54），并且响应于发射波特率时钟（50）之间的相位差产生相位误差信号（mu'）， 和接收波特率时钟（86）。 基站发射机（20）被配置为向用户单元接收机（26）发送相位误差信号（mu'）。 用户单元发射器（28）包含被配置为响应于相位误差信号调整发射波特率时钟（50）的相位的内插器（122）。
-
公开(公告)号：US06442217B1
公开(公告)日：2002-08-27
申请号：US09576220
申请日：2000-05-22
申请人： Bruce A. Cochran
发明人： Bruce A. Cochran
IPC分类号： H04L2722
CPC分类号： H04L27/3863 , H04L2027/0036 , H04L2027/0038
摘要： A communication system (10) includes a transmitter (12) which induces in a communication signal (16), a first component of in-phase to quadrature phase (I-Q) imbalance and a receiver (14) which adds a second component of I-Q imbalance. A digital, intermediate frequency (IF) I-Q balancer (38) compensates for the receiver-induced I-Q imbalance so that total distortion is sufficiently diminished and a data directed carrier tracking loop (60) may then perform carrier synchronization to generate a baseband signal (70). An adaptive equalizer (64) within the carrier tracking loop (60) may then effectively operate to compensate for additional distortions, such as the transmitter-induced I-Q imbalance.
摘要翻译： 通信系统（10）包括在通信信号（16）中引入同步到正交相位（IQ）不平衡的第一分量的发射机（12）和增加IQ不平衡的第二分量的接收机（14） 。 数字，中频（IF）IQ平衡器（38）补偿接收机引起的IQ不平衡，使得总失真被充分减小，并且数据导向载波跟踪环路（60）然后可以执行载波同步以产生基带信号（70 ）。 然后可以有效地操作载波跟踪环路（60）内的自适应均衡器（64）来补偿诸如发射机诱导的I-Q不平衡之类的附加失真。
-
7.发明授权公开(公告)号：US06363124B1
公开(公告)日：2002-03-26
申请号：US09680877
申请日：2000-10-06
申请人： Bruce A. Cochran
发明人： Bruce A. Cochran
IPC分类号： H04L2706
CPC分类号： H04L5/06 , H04L27/0014 , H04L2027/0046
摘要： A phase-noise compensated digital communication receiver (40, 40′, 40″) includes a carrier tracking loop (56) which imposes a transport delay on a carrier tracking loop signal (60) before that signal (60) is fed back upon itself. The carrier tracking loop (56) includes a phase rotator (58) that rotates a down-converted digital communication signal (50) by a phase determined by a phase-conveying signal (72). A carrier tracking loop signal is obtained from the carrier tracking loop and delayed in a delay element (82) by a duration that compensates for the transport delay. A phase rotator (84) then rotates the delayed carrier tracking loop signal through a phase value determined by the phase-conveying signal (72) to obtain an open-loop phase signal (86) from which data are extracted. Different embodiments of the receiver (40, 40′, 40″) are provided to accommodate adaptive equalizer (54) issues.
摘要翻译： 相位噪声补偿数字通信接收器（40,40'，40“）包括载波跟踪环路（56），该载波跟踪环路（56）在该信号（60）反馈到载波跟踪环路信号（60）之前对载波跟踪环路信号（60）施加传输延迟 本身。 载波跟踪环路（56）包括相位旋转器（58），该相位旋转器使下转换的数字通信信号（50）旋转相位由相位传送信号（72）确定的相位。 从载波跟踪环路获得载波跟踪环路信号并在延迟元件（82）中延迟持续时间，以补偿传输延迟。 相位旋转器（84）然后通过由相位传递信号（72）确定的相位值来旋转延迟的载波跟踪环路信号，以获得提取数据的开环相位信号（86）。 提供接收机（40,40'，40“）的不同实施例以适应自适应均衡器（54）问题。
-
8.发明授权Digital communications modulator having an interpolator upstream of a linearizer and method therefor 失效具有线性化器上游的内插器的数字通信调制器及其方法公开(公告)号：US06362701B1
公开(公告)日：2002-03-26
申请号：US09709885
申请日：2000-11-09
IPC分类号： H04L2720
CPC分类号： H04L25/03834 , H04L27/2071
摘要： An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
摘要翻译： IC调制处理器（28）可以被配置为以单芯片模式操作以适应处理器（28）的最大时钟速率的波特率，并且以双芯片模式适应超过最大时钟速率的波特率 。 IC调制处理器（28）对传送输入数据流（22）的通信信号执行数字处理。 在相位映射器（50）之后提供脉冲整形滤波器（54-57）。 脉冲整形滤波器（54-57）被实现为一对半滤波器。 在双芯片模式下，脉冲整形分布在两个IC调制处理器（28）之间。 内插器（86）和线性化器（106）跟随脉冲整形滤波器（54-57）。
-
9.发明授权
公开(公告)号：US5440265A
公开(公告)日：1995-08-08
申请号：US306112
申请日：1994-09-14
CPC分类号： H04L1/0059 , H04L1/20 , H04L27/22 , H04L7/046
摘要： Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops. Two phase locked loops (110, 112) operate in parallel but with initial reference phase offsets so that at least one of the two loops will not experience hang-up.
摘要翻译： 突发（12）的符号（18）被细分为符号部分（20）。 每个符号部分（20）被采样并转换成极坐标。 缓冲器组（38）可选地延迟样本并重播前导码（14）。 解调块（40）包括相干解调（58）和几个差分解调（60）。 每个差分解调器（60）处理它自己的符号段（20）流。 差分解调器（60）馈送前导码检测器（66）和符号同步电路（62）。 符号同步电路（62）识别产生最小频率误差幅度的符号部分（20）。 该符号部分（20）由相干解调（58）处理以获取载波相位并恢复数据。 相位解调（58）在相位域中实现，使得只需要在锁相环中产生振荡信号相位数据。 两个锁相环（110,112）并联操作，但具有初始参考相位偏移，使得两个回路中的至少一个不会经历挂起。
-
10.再颁专利公开(公告)号：USRE41380E1
公开(公告)日：2010-06-15
申请号：US10718507
申请日：2003-11-19
CPC分类号： H04L25/03834 , H04B1/717 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627 , H04L27/3411 , H04L27/3494 , H04L27/363
摘要： A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies the constrained-envelope signal stream (112) and transmits it as a radio-frequency broadcast signal (26).
摘要翻译： 一种限制包络数字通信发射机电路（22），其中二进制数据源（32）提供输入信号流（34），相位映射器（44）将输入信号流（34）映射到正交相位点 信号流（50），每单位波特间隔（64）具有预定数量的符号，并且在相位点星座（46）中定义相位点（54），脉冲扩展滤波器（76）对相位点信号 流（50）转换成经滤波的信号流（74），约束包络发生器（106）从经滤波的信号流（74）产生约束带宽误差信号流（108），延迟元件（138） 信号流（74）转换成与受约束带宽误差信号流（108）同步的延迟信号流（140），复数求和电路（110）将延迟信号流（140）和约束带宽误差信号流 108）到约束包络信号流（112）中，并且基本上是线性的 放大器（146）放大约束包络信号流（112）并将其作为射频广播信号（26）发送。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.025 秒)
