公开(公告)号：US20050280121A1

公开(公告)日：2005-12-22

申请号：US10872605

申请日：2004-06-21

申请人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

发明人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：US20080020521A1

公开(公告)日：2008-01-24

申请号：US11866786

申请日：2007-10-03

申请人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

发明人： Bruce Doris ,  Meikei Ieong ,  Edward Nowak ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：US20070108536A1

公开(公告)日：2007-05-17

申请号：US11164215

申请日：2005-11-15

申请人： MeiKei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

发明人： MeiKei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

IPC分类号： H01L21/8244

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66818 ,  H01L29/785

摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

摘要翻译： 提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。 本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。 本发明还涉及利用本发明的方法形成的所得半导体结构。

公开(公告)号：US20050221543A1

公开(公告)日：2005-10-06

申请号：US11125063

申请日：2005-05-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：US20070254438A1

公开(公告)日：2007-11-01

申请号：US11774663

申请日：2007-07-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

摘要翻译： 一种形成晶体管的方法。 提供半导体衬底。 图案化半导体衬底以提供第一本体边缘。 在第一身体边缘附近提供第一费米能级的第一门结构。 图案化半导体衬底以提供第二本体边缘。 半导体衬底的第一和第二主体边缘限定晶体管体。 在第二身体边缘附近设置第二费米能级的第二门结构。 在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

公开(公告)号：US20080042202A1

公开(公告)日：2008-02-21

申请号：US11874753

申请日：2007-10-18

申请人： Meikei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

发明人： Meikei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

IPC分类号： H01L27/12

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66818 ,  H01L29/785

摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

摘要翻译： 提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。 本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。 本发明还涉及利用本发明的方法形成的所得半导体结构。

公开(公告)号：US20120119681A1

公开(公告)日：2012-05-17

申请号：US12946682

申请日：2010-11-15

申请人： Ken Seidl ,  Edward Nowak ,  Paul Li

发明人： Ken Seidl ,  Edward Nowak ,  Paul Li

IPC分类号： H05B37/00

CPC分类号： H05B37/0272

摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.

摘要翻译： 本发明提供了自动打开和/或关闭相关设备的开关和传感器。 特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

公开(公告)号：US20080113476A1

公开(公告)日：2008-05-15

申请号：US12014850

申请日：2008-01-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20080042205A1

公开(公告)日：2008-02-21

申请号：US11877865

申请日：2007-10-24

申请人： Edward Nowak

发明人： Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/743 ,  H01L21/84 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/6675 ,  H01L29/78636 ,  H01L29/78648 ,  Y10S438/914

摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

摘要翻译： 提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。 还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。 该方法包括在基板的上表面形成开口。 此后，通过开口在衬底中形成掺杂剂区域。 根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。 接下来，在开口内形成具有至少一部分的前门导体。

公开(公告)号：US20070293031A1

公开(公告)日：2007-12-20

申请号：US11847384

申请日：2007-08-30

申请人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

发明人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。