公开(公告)号：US5619408A

公开(公告)日：1997-04-08

申请号：US387145

申请日：1995-02-10

申请人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

发明人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

IPC分类号： G06F9/30 ,  G06F9/318 ,  G05B15/00

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

公开(公告)号：US5748645A

公开(公告)日：1998-05-05

申请号：US654981

申请日：1996-05-29

申请人： Craig C. Hunter ,  Russell A. Reininger

发明人： Craig C. Hunter ,  Russell A. Reininger

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318552

摘要： A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.

摘要翻译： 基于扫描的测试方法从单个输入时钟（GCLK）生成常规功能时钟（CLK1和CLK2）和测试时钟（CLKA和CLKB）。 该方法允许根据其设计的集成电路（10）在部件的工作频率下进行测试。 此外，测试方法与已知的测试方法兼容，例如电平敏感扫描设计（“LSSD”）。 测试程序和设备的预先存在的主体可以与包含本发明的电路一起使用。 单一时钟要求也简化了设计。

公开(公告)号：US5119485A

公开(公告)日：1992-06-02

申请号：US351898

申请日：1989-05-15

申请人： William B. Ledbetter, Jr. ,  Russell A. Reininger

发明人： William B. Ledbetter, Jr. ,  Russell A. Reininger

IPC分类号： G06F12/08

CPC分类号： G06F12/0835

摘要： A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

摘要翻译： 一种用于通过备用总线主机在存储器访问期间保持回写高速缓存和主存储器之间的一致性的总线监听控制方法。 该方法和装置包括在存储器读取操作期间将“脏”或改变的数据从回写高速缓存提供给备用总线主机的选项，并且同时使来自回写高速缓存的“脏”或改变的数据无效。 该方法使由备用总线主机发起的页面输出/页面序列期间在高速缓存和主存储器之间维持一致性所需的高速缓存访​​问数量最小化，从而提高系统性能。

公开(公告)号：US5155824A

公开(公告)日：1992-10-13

申请号：US351899

申请日：1989-05-15

申请人： Robin W. Edenfield ,  William B. Ledbetter, Jr. ,  Russell A. Reininger

发明人： Robin W. Edenfield ,  William B. Ledbetter, Jr. ,  Russell A. Reininger

IPC分类号： G06F12/08

CPC分类号： G06F12/0804

摘要： A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

公开(公告)号：US5075846A

公开(公告)日：1991-12-24

申请号：US414335

申请日：1989-09-29

申请人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

发明人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F12/0877 ,  G06F9/3834

摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

摘要翻译： 提供了具有基于页面的序列化属性的数据处理器。 一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。 数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。 功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。 访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。 当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。 所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。 然后完成推迟的序列化访问。