公开(公告)号：US5155824A

公开(公告)日：1992-10-13

申请号：US351899

申请日：1989-05-15

申请人： Robin W. Edenfield ,  William B. Ledbetter, Jr. ,  Russell A. Reininger

发明人： Robin W. Edenfield ,  William B. Ledbetter, Jr. ,  Russell A. Reininger

IPC分类号： G06F12/08

CPC分类号： G06F12/0804

摘要： A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

公开(公告)号：US5075846A

公开(公告)日：1991-12-24

申请号：US414335

申请日：1989-09-29

申请人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

发明人： Russell A. Reininger ,  William B. Ledbetter, Jr. ,  Robin W. Edenfield ,  Van B. Shahan ,  Ralph C. McGarity ,  Eric E. Quintana

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F12/0877 ,  G06F9/3834

摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

摘要翻译： 提供了具有基于页面的序列化属性的数据处理器。 一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。 数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。 功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。 访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。 当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。 所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。 然后完成推迟的序列化访问。

公开(公告)号：US5185694A

公开(公告)日：1993-02-09

申请号：US371343

申请日：1989-06-26

申请人： Robin W. Edenfield ,  Ralph McGarity ,  Russell Reininger ,  William B. Ledbetter, Jr. ,  Van B. Shahan

发明人： Robin W. Edenfield ,  Ralph McGarity ,  Russell Reininger ,  William B. Ledbetter, Jr. ,  Van B. Shahan

IPC分类号： G06F12/08 ,  G06F9/315 ,  G06F13/28

CPC分类号： G06F9/30032

摘要： A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

公开(公告)号：US5197144A

公开(公告)日：1993-03-23

申请号：US484592

申请日：1990-02-26

申请人： Robin W. Edenfield ,  William B. Ledbetter, Jr.

发明人： Robin W. Edenfield ,  William B. Ledbetter, Jr.

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F2212/1032

摘要： A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selected for replacement are marked dirty, the cache controller "pushes" the cache line or dirty portions thereof into a buffer, which stores the cache line pending completion, by a bus interface controller, or the burst line read. When the burst line read terminates abnormally, due to a bus error or bus cache inhibit (or any other reason), the data cache controller reloads the copy-back cache with the cache line stored in the buffer. The reloading of the copy-back cache avoids the potential for multiple concurrent exception conditions, and eliminates the problem of unnecessarily removing an otherwise valid cache entry from the cache.

公开(公告)号：US5119485A

公开(公告)日：1992-06-02

申请号：US351898

申请日：1989-05-15

申请人： William B. Ledbetter, Jr. ,  Russell A. Reininger

发明人： William B. Ledbetter, Jr. ,  Russell A. Reininger

IPC分类号： G06F12/08

CPC分类号： G06F12/0835

摘要： A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

摘要翻译： 一种用于通过备用总线主机在存储器访问期间保持回写高速缓存和主存储器之间的一致性的总线监听控制方法。 该方法和装置包括在存储器读取操作期间将“脏”或改变的数据从回写高速缓存提供给备用总线主机的选项，并且同时使来自回写高速缓存的“脏”或改变的数据无效。 该方法使由备用总线主机发起的页面输出/页面序列期间在高速缓存和主存储器之间维持一致性所需的高速缓存访​​问数量最小化，从而提高系统性能。

公开(公告)号：US5477076A

公开(公告)日：1995-12-19

申请号：US297280

申请日：1994-08-29

申请人： James G. Gay ,  William B. Ledbetter, Jr.

发明人： James G. Gay ,  William B. Ledbetter, Jr.

IPC分类号： H01L23/58 ,  G01K7/00 ,  G01K7/01 ,  H01L23/34 ,  H01L27/02 ,  H01L31/058 ,  H01L23/48

CPC分类号： H01L27/0248 ,  G01K7/01 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).

摘要翻译： 集成电路实现片上热电路（12），用于通过仅需要一个专用集成电路引脚（16）来测量工作集成电路管芯（10）的温度。 第二集成电路引脚（18）被使用，但是也被连接成直接连接到集成电路上的其它电路（14），并且被其他电路用于测量集成电路管芯温度的同时。 在一种形式中，第二集成电路引脚是接地端子。 耦合到接地端子的误差电压可以由外部差分放大器（24）从温度计算中去除。

公开(公告)号：US5294845A

公开(公告)日：1994-03-15

申请号：US931187

申请日：1992-08-17

申请人： Steven C. McMahan ,  Kenneth C. Scheuer ,  William B. Ledbetter, Jr. ,  Michael G. Gallup ,  James G. Gay

发明人： Steven C. McMahan ,  Kenneth C. Scheuer ,  William B. Ledbetter, Jr. ,  Michael G. Gallup ,  James G. Gay

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/003

CPC分类号： H03K19/017581 ,  H03K19/0005

摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有比第一输出缓冲器更低的输出阻抗的第二输出缓冲器可以与第一输出缓冲器并联选择性地耦合，以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。

公开(公告)号：US5162672A

公开(公告)日：1992-11-10

申请号：US632901

申请日：1990-12-24

申请人： Steven C. McMahan ,  Kenneth C. Scheuer ,  William B. Ledbetter, Jr. ,  Michael G. Gallup ,  James G. Gay

发明人： Steven C. McMahan ,  Kenneth C. Scheuer ,  William B. Ledbetter, Jr. ,  Michael G. Gallup ,  James G. Gay

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/017581 ,  H03K19/0005

摘要： A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance then the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

摘要翻译： 数据处理器具有至少一个输出端，数据处理器的用户可以根据数据处理器的应用环境来改变其输出阻抗。 输出缓冲级的第一输出缓冲器具有预定的输出阻抗，并且耦合在级的输入端和输出端子之间。 第一输出缓冲器提供第一输出端阻抗。 具有较低输出阻抗的第二输出缓冲器然后与第一输出缓冲器可以被选择性地耦合到第一输出缓冲器以减小输出端子的输出阻抗。 输出缓冲器的耦合由数据处理器的用户控制，数据处理器的用户提供用于选择多个预定输出端子阻抗值之一的控制输入。

公开(公告)号：US5086407A

公开(公告)日：1992-02-04

申请号：US361539

申请日：1989-06-05

申请人： Ralph C. McGarity ,  William B. Ledbetter, Jr. ,  Steven C. McMahan ,  Michael G. Gallup ,  Russell Stanphill ,  James G. Gay

发明人： Ralph C. McGarity ,  William B. Ledbetter, Jr. ,  Steven C. McMahan ,  Michael G. Gallup ,  Russell Stanphill ,  James G. Gay

IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F13/4208 ,  G06F15/7832

摘要： A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

摘要翻译： 具有可被编程为将电路的地址和数据总线端子置于两种模式之一的输入的单芯片数据处理器集成电路。 在第一或多路复用模式下，电路的地址和数据终端直接连接，并且当两者都写入外部电路时，地址位与数据位进行时分复用。 在第二或正常模式下，电路的地址和数据端子不连接，地址位与电路无关地与电路通信的数据位通信。 需要集成电路外部的电路来实现复用模式。 控制部分确保当电路处于复用模式时避免位冲突。

公开(公告)号：US5666509A

公开(公告)日：1997-09-09

申请号：US216998

申请日：1994-03-24

申请人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

发明人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0888 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/1027

摘要： A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

摘要翻译： 处理器（10）具有数据高速缓存单元（16），其中数据高速缓存单元包括存储器管理单元（MMU）（32）。 MMU包含存储或产生高速缓存模式（CM）位的透明转换寄存器（TTR），地址转换高速缓冲存储器（40）或表格移动控制器（42）内的存储单元，其指示存储器访问（即，写入 操作）精确或不准确。 精确的操作要求执行第一个写入操作或总线写入指令，直到第一个操作/指令完成或不存在故障，才执行其他操作/指令。 不精确的操作是可以与其他指令同时排队，部分执行或执行的操作/指令，而不管故障或总线写操作。 通过允许逻辑地址来确定总线写操作是精确还是不准确，实现了大量的系统灵活性。