公开(公告)号：US20050253836A1

公开(公告)日：2005-11-17

申请号：US10980201

申请日：2004-11-03

申请人： Byoung Kim ,  Kyoung Lee

发明人： Byoung Kim ,  Kyoung Lee

IPC分类号： G02F1/133 ,  G02F1/1362 ,  G09F9/35 ,  G09G3/36 ,  G09G5/00

CPC分类号： G02F1/136286 ,  G09G3/3655 ,  G09G2300/043 ,  G09G2320/0209

摘要： A liquid crystal display (LCD) device is provided which includes an LCD panel having first and second substrates facing each other, a plurality of gate and data lines crossing each other to define a plurality of pixel regions; a common electrode; a coupling line perpendicular to the data lines, to generate a signal by a coupling phenomenon with the data lines; and a common voltage generation circuit and a common voltage compensation circuit receiving the signal from the coupling line for compensating the common voltage. The compensated common voltage is applied to the common electrode.

摘要翻译： 提供了一种液晶显示器（LCD）装置，其包括具有彼此面对的第一和第二基板的LCD面板，多个栅极和数据线彼此交叉以限定多个像素区域; 公共电极; 垂直于数据线的耦合线，通过与数据线的耦合现象产生信号; 以及公共电压产生电路和公共电压补偿电路，接收来自耦合线的信号以补偿公共电压。 补偿的公共电压施加到公共电极。

公开(公告)号：US20080053694A1

公开(公告)日：2008-03-06

申请号：US11850142

申请日：2007-09-05

申请人： Hong Park ,  Kyoung Lee ,  Hae Jung

发明人： Hong Park ,  Kyoung Lee ,  Hae Jung

IPC分类号： H05K9/00

CPC分类号： H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/09781

摘要： Provided is a guard trace pattern reducing far-end crosstalk and a printed circuit board having the guard trace pattern. The guard trace pattern includes a first guard trace pattern parallel with two signal lines and a plurality of second guard trace patterns perpendicular to the first guard trace pattern to increase mutual capacitance between the two signal lines and the guard trace pattern and increase mutual capacitance between the two signal lines. The printed circuit board includes the aforementioned guard trace pattern disposed between micro strip transmission lines. A characteristic impedance of the guard trace pattern is different from a characteristic impedance of the micro strip transmission lines, and resistances having the same value as a resistance component value of the characteristic impedance of the guard trace pattern are provided to both ends of the guard trace pattern.

摘要翻译： 提供了减少远端串扰的保护迹线图案和具有保护迹线图案的印刷电路板。 保护迹线图形包括与两条信号线平行的第一保护迹线图形和垂直于第一保护迹线图形的多个第二保护迹线图案，以增加两个信号线和保护迹线图案之间的互电容，并增加两个信号线之间的互电容 两条信号线。 印刷电路板包括设置在微带传输线之间的上述保护迹线图案。 保护迹线图案的特性阻抗与微带传输线的特性阻抗不同，并且具有与保护迹线图案的特性阻抗的电阻分量值相同值的电阻提供给保护迹线的两端 模式。

公开(公告)号：US20050140403A1

公开(公告)日：2005-06-30

申请号：US10879524

申请日：2004-06-30

申请人： Kyoung Lee

发明人： Kyoung Lee

IPC分类号： G11C29/00 ,  H03B19/00 ,  H03K5/00

CPC分类号： H03K5/00006

摘要： An internal clock doubler comprises a clock delay unit, an edge detecting unit and an output driver. The clock delay unit delays a clock signal for a predetermined delay time and outputs a delay clock signal. The edge detecting unit detects rising and falling edges of the clock signal in response to the delay clock signal and outputs a rising pulse signal and a falling pulse signal. The output driver outputs a double clock signal toggled at every rising edge and every falling edge of the clock signal in response to the rising pulse signal and the falling pulse signal. As a result, since a double clock signal having double frequency of an internal clock signal is generated without external input of an additional clock signal through an additional pad, a stable high-speed test can be performed on a semiconductor memory device.

摘要翻译： 内部时钟倍频器包括时钟延迟单元，边缘检测单元和输出驱动器。 时钟延迟单元将时钟信号延迟预定的延迟时间并输出延迟时钟信号。 边沿检测单元响应于延迟时钟信号检测时钟信号的上升沿和下降沿，并输出上升脉冲信号和下降脉冲信号。 输出驱动器响应于上升脉冲信号和下降脉冲信号输出在时钟信号的每个上升沿和每个下降沿切换的双时钟信号。 结果，由于在内部时钟信号具有双倍频率的双时钟信号通过附加焊盘产生附加时钟信号的外部输入，所以可以对半导体存储器件执行稳定的高速测试。

公开(公告)号：US20070170432A1

公开(公告)日：2007-07-26

申请号：US11716690

申请日：2007-03-12

申请人： Kyoung Lee ,  Seung Nam ,  Jae Oh

发明人： Kyoung Lee ,  Seung Nam ,  Jae Oh

IPC分类号： H01L29/76

CPC分类号： H01L27/124 ,  G02F1/1362 ,  G02F2001/136236 ,  H01L27/1288 ,  H01L29/66765

摘要： A thin film transistor array substrate includes a gate line formed on a substrate, a data line formed on the substrate intersecting with the gate line to define a pixel region, a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor layer formed on the gate insulating layer,an ohmic contact layer on the semiconductor layer, and a source electrode and a drain electrode on the ohmic contact layer, and a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor, wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode material, and covering the gate line.

摘要翻译： 薄膜晶体管阵列基板包括形成在基板上的栅极线，形成在与栅极线交叉以限定像素区域的基板上的数据线，形成在栅极线和数据线的交叉处的薄膜晶体管， 所述薄膜晶体管包括形成在所述基板上的栅极电极，形成在所述栅极电极和所述基板上的栅极绝缘层，形成在所述栅极绝缘层上的半导体层，所述半导体层上的欧姆接触层以及源电极和 漏极电极和像素区域内的透明电极材料，并连接到薄膜晶体管的漏电极，其中栅极绝缘层包括位于数据线下方的栅绝缘图案和透明电极材料，以及 覆盖门线。

公开(公告)号：US20060022969A1

公开(公告)日：2006-02-02

申请号：US11187050

申请日：2005-07-21

申请人： Kyoung Lee ,  Ki Eom ,  Jin Choi

发明人： Kyoung Lee ,  Ki Eom ,  Jin Choi

IPC分类号： G09G5/00

CPC分类号： G09G3/32 ,  G02F1/136286 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/02

摘要： A light emitting display includes a substrate, a pixel area, a first power source line to supply a first power signal to each pixel on a first side of the pixel area, a second power source line to supply the first power signal to each pixel on a second side of the pixel area, and an impedance compensator for compensating a difference in a voltage drop between the first power source line and the second power source line. A voltage drop caused by line resistance that depends on the length of the first and second power source line that supply the first power signal to a lower and upper side of a pixel area, respectively, is equalized, thereby minimizing the voltage drop of the first power signal supplied to all pixels, and minimizing non-uniformity of brightness due to the voltage drop differences at each pixel.

摘要翻译： 发光显示器包括：衬底，像素区域，用于向像素区域的第一侧上的每个像素提供第一功率信号的第一电源线;将第一功率信号提供给每个像素的第二电源线; 像素区域的第二侧，以及用于补偿第一电源线和第二电源线之间的电压降差的阻抗补偿器。 由线电阻引起的电压降分别取决于将第一功率信号提供给像素区域的下侧和上侧的第一和第二电源线的长度，从而最小化第一 功率信号提供给所有像素，并且由于每个像素处的电压降差异使亮度的不均匀性最小化。

公开(公告)号：US20070045123A1

公开(公告)日：2007-03-01

申请号：US11216686

申请日：2005-08-31

申请人： Duk Hong ,  Kyoung Lee ,  Markus Naujok ,  Roman Knoefler

发明人： Duk Hong ,  Kyoung Lee ,  Markus Naujok ,  Roman Knoefler

IPC分类号： C25D5/02

CPC分类号： C25D5/022 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.

摘要翻译： 形成金属互连层的方法包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后在邻近接触孔的位置在电绝缘层中形成凹陷。 然后用第一导电材料（例如，钨（W））填充接触孔和凹部。 然后露出接触孔内的第一导电材料的至少一部分。 通过使用接触孔内部和凹部内的第一导电材料作为蚀刻掩模来蚀刻电绝缘层的一部分而发生该曝光。 然后移除凹槽内的第一导电材料以露出电绝缘层的另一部分。 之后，第一导电材料的暴露部分被直接接触第一导电材料的暴露部分的第二导电材料（例如铜（Cu））覆盖。 该覆盖步骤导致包括第一和第二导电材料的布线图案的定义。

公开(公告)号：US20070018169A1

公开(公告)日：2007-01-25

申请号：US11452785

申请日：2006-06-14

申请人： Kyoung Lee ,  Jae Oh ,  Kye Song

发明人： Kyoung Lee ,  Jae Oh ,  Kye Song

IPC分类号： H01L29/04

CPC分类号： H01L29/41758 ,  G02F1/136259 ,  G02F2001/136263

摘要： A liquid crystal display device and its fabrication method may prevent occurrence of light leakage generated from the sides of a data line. A dummy pattern at sides of the data line with glass powder as an insulation film may simplify the repairing process. A method for fabricating a liquid crystal display device includes a gate electrode, a gate line, a dummy pattern and a first insulation film that are formed on a substrate. A switching element is formed on a portion of the gate electrode and includes a source electrode, a drain electrode and an active layer. A data line formed at a portion of the dummy pattern. A second insulation film is formed on the substrate and has a first contact hole that exposes a portion of the drain electrode. A pixel electrode is formed on the substrate and is electrically connected with the drain electrode through the first contact hole.

摘要翻译： 液晶显示装置及其制造方法可以防止从数据线的侧面产生的漏光的发生。 在玻璃粉末作为绝缘膜的数据线侧面的虚拟图案可以简化修复过程。 一种制造液晶显示装置的方法包括形成在基板上的栅电极，栅极线，虚设图案和第一绝缘膜。 开关元件形成在栅电极的一部分上，并且包括源电极，漏电极和有源层。 形成在虚拟图案的一部分的数据线。 在基板上形成第二绝缘膜，并且具有暴露出漏电极的一部分的第一接触孔。 像素电极形成在基板上，并通过第一接触孔与漏电极电连接。

公开(公告)号：US20060243980A1

公开(公告)日：2006-11-02

申请号：US11118496

申请日：2005-05-02

申请人： Kyoung Lee ,  Jae Oh

发明人： Kyoung Lee ,  Jae Oh

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/133514 ,  G02F1/13458 ,  G02F1/1362 ,  H01L27/1288

摘要： A liquid crystal display panel includes: a thin film transistor array substrate having a gate line and a data line provided on the substrate; a gate insulating film between the gate line and the data line; a thin film transistor having a source electrode, a drain electrode and a gate electrode; a pixel electrode; a protective film for protecting the thin film transistor; a plurality of pads; a transparent electrode pattern formed on the data line, source electrode and drain electrode; and a color filter array substrate joined to the thin film transistor array substrate so that the color filter substrate does not overlap the pad area of the thin film transistor array substrate, wherein at least one of the gate insulating film and protective film in the pad area is etched using the color filter array substrate as a mask to expose at least one of the plurality of pads.

公开(公告)号：US20080029501A1

公开(公告)日：2008-02-07

申请号：US11596108

申请日：2005-05-12

申请人： Kyoung Lee

发明人： Kyoung Lee

IPC分类号： B23K9/00

CPC分类号： B23K26/147 ,  B23K26/146 ,  B23K26/211 ,  B23K31/02

摘要： The present invention relates to a high energy density beam welding system using molten metal droplet jetting. The present invention includes a beam emitting unit for emitting a high energy density beam onto a welded portion on a target object; and a molten metal droplet jetting unit for generating molten metal droplets to transfer or spray the molten metal droplets onto the welded portion on the target object, which follows a path of the beam emitting unit. Thus, it has advantages of widening a range of applications and enhancing the productivity and the quality in that a welding can be performed at a high junction efficiency even where a gap is wide, a loss in the high density energy beam is small, and heat distortions of the welded portion can be minimized.

摘要翻译： 本发明涉及使用熔融金属液滴喷射的高能量密度束焊接系统。 本发明包括用于将高能量密度束发射到目标物体上的焊接部分上的光束发射单元; 以及熔融金属液滴喷射单元，用于产生熔融金属液滴，以将熔融金属液滴转移或喷射到跟随射束发射单元的路径的目标物体上的焊接部分上。 因此，具有扩大应用范围和提高生产率和质量的优点，即，即使在间隙较宽，高密度能量束的损耗小的情况下也可以以高结合效率进行焊接，并且热量 焊接部分的变形可以最小化。

公开(公告)号：US20070072406A1

公开(公告)日：2007-03-29

申请号：US11237987

申请日：2005-09-28

申请人： Kyoung Lee ,  Ja-Hum Ku ,  Duk Hong ,  Wan Park

发明人： Kyoung Lee ,  Ja-Hum Ku ,  Duk Hong ,  Wan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

摘要： Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

摘要翻译： 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。