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    SYSTEM FOR AUTHENTICATION MANAGEMENT OF A SENSOR NODE HAVING A SUBSCRIPTION PROCESSING FUNCTION, AND A METHOD FOR OPERATING THE SYSTEM
    3.
    发明申请
    SYSTEM FOR AUTHENTICATION MANAGEMENT OF A SENSOR NODE HAVING A SUBSCRIPTION PROCESSING FUNCTION, AND A METHOD FOR OPERATING THE SYSTEM 审中-公开
    具有认购加工功能的传感器节点的认证管理系统和操作系统的方法

    公开(公告)号：US20130067544A1

    公开(公告)日：2013-03-14

    申请号：US13699332

    申请日：2011-05-24

    申请人： Gwang Hoon Kwark ,  Tae Hoon Kim ,  Byung Kwon Park ,  Hyung Rim Choi

    发明人： Gwang Hoon Kwark ,  Tae Hoon Kim ,  Byung Kwon Park ,  Hyung Rim Choi

    IPC分类号： H04L9/32

    CPC分类号： H04W12/08 ,  H04L9/321 ,  H04L63/0281 ,  H04L63/10 ,  H04L67/12 ,  H04L2209/805

    摘要： The present invention relates to a system for authentication management of a sensor node having a subscription processing function, and a method for operating the system. Upon receiving information about a sensor node allocated with an IP address, the system supports the access of only authorized user equipment to a corresponding sensor node, which blocking any direct access of unauthorized user equipment to the sensor node, thereby strengthening the security of the sensor node. According to the present invention, a relay server receives subscription information from user equipment. The relay server checks permission validity of corresponding user equipment. If the user equipment has a valid permission, the relay server transmits the subscription information to a sensor node, and transmits subscription acceptance information to the user equipment. Then the sensor node transmits the collected and stored information to the user equipment having a valid permission.

    摘要翻译： 本发明涉及具有订阅处理功能的传感器节点的认证管理系统和用于操作系统的方法。 在接收到分配有IP地址的传感器节点的信息时，系统仅支持授权用户设备到对应的传感器节点的访问，该传感器节点阻止非法用户设备直接访问传感器节点，从而加强传感器的安全性 节点。 根据本发明，中继服务器从用户设备接收订阅信息。 中继服务器检查相应用户设备的许可有效性。 如果用户设备具有有效许可，则中继服务器向订阅节点发送订阅信息，并向用户设备发送订阅接受信息。 然后传感器节点将收集和存储的信息发送给具有有效许可的用户设备。

    Circuit for testing word line of semiconductor memory device
    5.
    发明授权
    Circuit for testing word line of semiconductor memory device 有权
    半导体存储器件字线测试电路

    公开(公告)号：US07573764B2

    公开(公告)日：2009-08-11

    申请号：US11824843

    申请日：2007-06-29

    申请人： Byung Kwon Park

    发明人： Byung Kwon Park

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C8/08 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/1802 ,  G11C2029/5006

    摘要： A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode signals and a word line test signal, a first address predecoder configured to output first address information signals having first address information in response to the second test signal and a first address signal, and a second address predecoder configured to output second address information signals having second address information in response to the first test signals and second address signals.

    摘要翻译： 提供了一种用于测试半导体存储器件的字线的电路，其包括：第一测试信号发生器，被配置为响应于测试模式信号产生第一测试信号;第二测试信号发生器，被配置为响应于所述第二测试信号 测试模式信号和字线测试信号，第一地址预解码器被配置为响应于第二测试信号和第一地址信号输出具有第一地址信息的第一地址信息信号，以及第二地址预解码器，被配置为输出第二地址信息信号 具有响应于第一测试信号和第二地址信号的第二地址信息。

    Circuit for testing word line of semiconductor memory device
    6.
    发明申请
    Circuit for testing word line of semiconductor memory device 有权
    半导体存储器件字线测试电路

    公开(公告)号：US20080159029A1

    公开(公告)日：2008-07-03

    申请号：US11824843

    申请日：2007-06-29

    申请人： Byung Kwon Park

    发明人： Byung Kwon Park

    IPC分类号： G11C29/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C8/08 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/1802 ,  G11C2029/5006

    摘要： A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode signals and a word line test signal, a first address predecoder configured to output first address information signals having first address information in response to the second test signal and a first address signal, and a second address predecoder configured to output second address information signals having second address information in response to the first test signals and second address signals.

    摘要翻译： 提供了一种用于测试半导体存储器件的字线的电路，其包括：第一测试信号发生器，被配置为响应于测试模式信号产生第一测试信号;第二测试信号发生器，被配置为响应于所述第二测试信号 测试模式信号和字线测试信号，第一地址预解码器被配置为响应于第二测试信号和第一地址信号输出具有第一地址信息的第一地址信息信号，以及第二地址预解码器，被配置为输出第二地址信息信号 具有响应于第一测试信号和第二地址信号的第二地址信息。