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    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES
    1.
    发明申请
    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 有权
    制造垂直半导体器件的方法

    公开(公告)号：US20120058629A1

    公开(公告)日：2012-03-08

    申请号：US13212485

    申请日：2011-08-18

    申请人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    发明人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    IPC分类号： H01L21/28 ,  H01L21/20

    CPC分类号： H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    摘要： Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    摘要翻译： 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    Methods of manufacturing vertical semiconductor devices
    2.
    发明授权
    Methods of manufacturing vertical semiconductor devices 有权
    制造垂直半导体器件的方法

    公开(公告)号：US08697524B2

    公开(公告)日：2014-04-15

    申请号：US13212485

    申请日：2011-08-18

    申请人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    发明人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    摘要： Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    摘要翻译： 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    Methods of forming non-volatile memory devices including dummy word lines
    4.
    发明授权
    Methods of forming non-volatile memory devices including dummy word lines 有权
    形成包括虚拟字线的非易失性存储器件的方法

    公开(公告)号：US08198157B2

    公开(公告)日：2012-06-12

    申请号：US13236913

    申请日：2011-09-20

    申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： G11C16/0483 ,  G11C16/3427

    摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

    Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines
    5.
    发明申请
    Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines 有权
    形成包含虚拟字线的非易失性存储器件的方法

    公开(公告)号：US20120045890A1

    公开(公告)日：2012-02-23

    申请号：US13236913

    申请日：2011-09-20

    申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    IPC分类号： H01L21/28

    CPC分类号： G11C16/0483 ,  G11C16/3427

    摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 还讨论了相关方法。

    FLASH MEMORY DEVICES
    8.
    发明申请
    FLASH MEMORY DEVICES 审中-公开
    闪存存储器件

    公开(公告)号：US20090212340A1

    公开(公告)日：2009-08-27

    申请号：US12392656

    申请日：2009-02-25

    申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

    发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/11521

    摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.

    摘要翻译： 一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸 其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

    NON-VOLATILE MEMORY DEVICES AND METHODS FOR FORMING THE SAME
    9.
    发明申请
    NON-VOLATILE MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
    非易失性存储器件及其形成方法

    公开(公告)号：US20070259505A1

    公开(公告)日：2007-11-08

    申请号：US11613329

    申请日：2006-12-20

    申请人： Young-Woo Park ,  Jung-Dal Choi

    发明人： Young-Woo Park ,  Jung-Dal Choi

    IPC分类号： H01L21/02

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11568

    摘要： Non-volatile memory devices and methods for forming the same are provided. A device isolation layer may be formed on the semiconductor substrate to define an active region. A tunneling insulation pattern, a charge storage pattern, and a blocking insulation pattern may be disposed on the active region. A gate electrode may be disposed on the blocking insulation pattern. The charge storage pattern may be arranged in a matrix and a lower surface thereof is higher than an upper surface of the device isolation layer.

    摘要翻译： 提供非易失性存储器件及其形成方法。 可以在半导体衬底上形成器件隔离层以限定有源区。 隧道绝缘图案，电荷存储图案和阻挡绝缘图案可以设置在有源区域上。 栅电极可以设置在阻挡绝缘图案上。 电荷存储图案可以布置成矩阵并且其下表面高于器件隔离层的上表面。

    Method of forming contacts for a bit line and a storage node in a semiconductor device
    10.
    发明授权
    Method of forming contacts for a bit line and a storage node in a semiconductor device 有权
    在半导体器件中形成位线和存储节点的触点的方法

    公开(公告)号：US06777343B2

    公开(公告)日：2004-08-17

    申请号：US10256438

    申请日：2002-09-26

    申请人： Young-Woo Park ,  Won-Sung Lee

    发明人： Young-Woo Park ,  Won-Sung Lee

    IPC分类号： H01L21302

    CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming self-aligned contact holes in an oxide layer to expose a semiconductor substrate between adjacent gate lines. The gate lines are formed such that a spacing between adjacent gate lines in the storage node contact region is equal to or greater than a spacing between adjacent gate lines in the bit line contact region. An insulating layer is deposited on the gate line to fill spaces between the gate lines. Self-aligned contact holes are formed in the insulating layer, using a photolithographic process. As a result, storage node contact hole not-opening phenomenon and bit line contact shoulder over-etching phenomenon can be avoided.

    摘要翻译： 在氧化物层中形成自对准接触孔以在相邻栅极线之间露出半导体衬底的方法。 栅极线形成为使得存储节点接触区域中的相邻栅极线之间的间隔等于或大于位线接触区域中的相邻栅极线之间的间隔。 绝缘层沉积在栅极线上以填充栅极线之间的空间。 使用光刻工艺在绝缘层中形成自对准的接触孔。 结果，可以避免存储节点接触孔不开现象和位线接触肩部过蚀刻现象。