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    Architectures for programmable logic devices
    1.
    发明授权
    Architectures for programmable logic devices 失效
    可编程逻辑器件的架构

    公开(公告)号：US5999016A

    公开(公告)日：1999-12-07

    申请号：US920298

    申请日：1997-08-28

    申请人： Cameron McClintock ,  Ninh Ngo ,  Risa Altaf ,  Richard G. Cliff

    发明人： Cameron McClintock ,  Ninh Ngo ,  Risa Altaf ,  Richard G. Cliff

    IPC分类号： H01L21/82 ,  H03K19/00 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 每个超区域可以像小型或中等尺寸的可编程逻辑器件，并且可以包括可编程逻辑区域的交叉行和列的二维阵列。 每个区域又可以包括多个可编程逻辑的子区域。 水平和垂直超超区域互连导体与超区域的行和列相关联。 这些导体可以选择性地连接到超区域中的水平和垂直的区域间互连导体。

    Power-on reset circuit with well-defined reassertion voltage
    2.
    发明授权
    Power-on reset circuit with well-defined reassertion voltage 失效
    上电复位电路具有明确的重新启动电压

    公开(公告)号：US5821787A

    公开(公告)日：1998-10-13

    申请号：US726461

    申请日：1996-10-04

    申请人： Cameron McClintock ,  Ninh Ngo

    发明人： Cameron McClintock ,  Ninh Ngo

    IPC分类号： H03K17/22

    CPC分类号： H03K17/223

    摘要： A power-on reset (POR) circuit (200) asserts a POR signal when the supply voltage (V.sub.CC) is turned on. As the supply voltage increases, the POR signal is deasserted when the supply voltage reaches a voltage (V.sub.POR1) sufficiently high to make storage elements in a controlled circuit fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough (V.sub.POR2) to render the storage elements in the controlled circuit incapable of holding accurate data. The V.sub.POR2 level that triggers the reassertion of the POR signal is lower than the V.sub.POR1. Additional circuitry insures that the POR signal is reasserted when V.sub.CC drops to the V.sub.POR2 level by sampling the transistor threshold voltages of the circuit. Another control signal allows the POR signal to be forcibly generated.

    摘要翻译： 当电源电压（VCC）导通时，上电复位（POR）电路（200）断言POR信号。 随着电源电压的增加，当电源电压达到足够高的电压（VPOR1）以使受控电路中的存储元件完全运行时，POR信号被置为无效。 POR信号保持断言，直到电源电压电平下降到足够低的水平（VPOR2），以使受控电路中的存储元件不能保存准确的数据。 触发POR信号重新置位的VPOR2电平低于VPOR1。 附加电路确保当VCC通过采样电路的晶体管阈值电压VCC降至VPOR2电平时，重置POR信号。 另一个控制信号允许强制产生POR信号。

    Configuration shift register
    4.
    发明授权
    Configuration shift register 有权
    配置移位寄存器

    公开(公告)号：US06842039B1

    公开(公告)日：2005-01-11

    申请号：US10278177

    申请日：2002-10-21

    申请人： Mario Guzman ,  Christopher Lane ,  Andy Lee ,  Ninh Ngo

    发明人： Mario Guzman ,  Christopher Lane ,  Andy Lee ,  Ninh Ngo

    IPC分类号： H03K19/177 ,  G01R31/28

    CPC分类号： H03K19/17752 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17756

    摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

    摘要翻译： 电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。 可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

    Configuration shift register
    6.
    发明授权
    Configuration shift register 有权
    配置移位寄存器

    公开(公告)号：US07112992B1

    公开(公告)日：2006-09-26

    申请号：US11008080

    申请日：2004-12-08

    申请人： Mario Guzman ,  Chris Lane ,  Andy L. Lee ,  Ninh Ngo

    发明人： Mario Guzman ,  Chris Lane ,  Andy L. Lee ,  Ninh Ngo

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17756

    摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.

    摘要翻译： 电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。 可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

    ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES
    7.
    发明申请
    ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES 有权
    对可编程逻辑资源的错误检测

    公开(公告)号：US20080052569A1

    公开(公告)日：2008-02-28

    申请号：US11930739

    申请日：2007-10-31

    申请人： Ninh Ngo ,  Andy Lee ,  Kerry Veenstra

    发明人： Ninh Ngo ,  Andy Lee ,  Kerry Veenstra

    IPC分类号： G06F11/00

    CPC分类号： H03K19/17764 ,  G06F11/1004

    摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

    摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method
    8.
    发明授权
    Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method 有权
    可编程逻辑器件具有可修复电路阵列内的不可修复电路区域和相关配置硬件和方法

    公开(公告)号：US07215140B1

    公开(公告)日：2007-05-08

    申请号：US10452673

    申请日：2003-05-30

    申请人： Rahul Saini ,  Andy Lee ,  Ninh Ngo

    发明人： Rahul Saini ,  Andy Lee ,  Ninh Ngo

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

    摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controlling shifting of programming data in normal and redundant modes for both dedicated block regions and fully repairable logic array regions during both regular and test programming sequences of a PLD. Other aspects provide circuitry and methods for interface routing between dedicated blocks and repairable logic array regions in both normal and redundant modes. Various other aspects are also disclosed.

    摘要翻译： 本发明的一个实施例提供一种可编程逻辑器件（“PLD”），其包括一个或多个可修复逻辑阵列区域内的一个或多个专用电路块。 本发明的方面提供用于在PLD的规则和测试编程序列期间控制专用块区域和完全可修复的逻辑阵列区域的正常和冗余模式中的编程数据的移位的电路和方法。 其他方面提供用于在正常模式和冗余模式中的专用块和可修复逻辑阵列区之间的接口路由的电路和方法。 还公开了各种其它方面。