公开(公告)号：US20110269294A1

公开(公告)日：2011-11-03

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20100197139A1

公开(公告)日：2010-08-05

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US07732341B2

公开(公告)日：2010-06-08

申请号：US11727124

申请日：2007-03-23

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08278221B2

公开(公告)日：2012-10-02

申请号：US13181655

申请日：2011-07-13

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US08003543B2

公开(公告)日：2011-08-23

申请号：US12759771

申请日：2010-04-14

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20080090419A1

公开(公告)日：2008-04-17

申请号：US11727124

申请日：2007-03-23

申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

公开(公告)号：US20080076070A1

公开(公告)日：2008-03-27

申请号：US11554324

申请日：2006-10-30

申请人： Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

发明人： Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

IPC分类号： G03F7/00

CPC分类号： H01L21/31144 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

摘要： A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.

摘要翻译： 通过在集成电路基板上形成牺牲图案，在集成电路基板上形成精细图案。 牺牲图案包括顶部和侧壁。 然后进行原子层沉积以在牺牲图案上沉积掩模材料层，包括在其顶部和侧壁上以及其间的集成电路基板上。 然后蚀刻原子层沉积的掩模材料层，以暴露其间的顶部和集成电路，使得掩模材料图案残留在侧壁上。 然后去除牺牲图案，然后通过保留的掩模材料图案蚀刻集成电路基板。

公开(公告)号：US07795099B2

公开(公告)日：2010-09-14

申请号：US11979748

申请日：2007-11-08

申请人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

发明人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

IPC分类号： H01L21/762

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

摘要翻译： 具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。 凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。 第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。

公开(公告)号：US07873935B2

公开(公告)日：2011-01-18

申请号：US11762838

申请日：2007-06-14

申请人： Sung-gon Jung ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

发明人： Sung-gon Jung ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

IPC分类号： G06F17/50 ,  G06F19/00 ,  G21K5/00

CPC分类号： G03F1/36

摘要： A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.

摘要翻译： 一种制造掩模的方法包括：设计第一掩模数据图案，设计用于形成第一掩模数据图案的第二掩模数据图案，使用基于布局的自对准方法获取从第二掩模数据图案预测的第一仿真图案， 对准双重图案（SADP）仿真，将第一仿真模式与第一掩模数据模式进行比较，并根据比较结果修改第二掩模数据模式。 该方法还包括在修改的第二掩模数据模式上执行光学邻近校正（OPC），从使用基于图像的SADP仿真的第二掩模数据模式中获取第二仿真模式，其中已经执行了OPC，并且比较 第二仿真模式和第一掩模数据模式，并且根据比较结果制造对应于已经执行了OPC的第二掩模数据模式的第一掩模层。

公开(公告)号：US20080105931A1

公开(公告)日：2008-05-08

申请号：US11979748

申请日：2007-11-08

申请人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

发明人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

摘要翻译： 具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。 凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。 第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。