公开(公告)号：US20110053362A1

公开(公告)日：2011-03-03

申请号：US12873574

申请日：2010-09-01

Applicant: Hyoung-Hee KIM ,  Yool Kang ,  Seong-Ho Moon ,  Seok-Hwan Oh ,  So-Ra Han ,  Seong-Woon Choi

Inventor： Hyoung-Hee KIM ,  Yool Kang ,  Seong-Ho Moon ,  Seok-Hwan Oh ,  So-Ra Han ,  Seong-Woon Choi

IPC: H01L21/28 ,  G03F7/20

CPC classification number: H01L21/28123 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11529

Abstract: A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns.

Abstract translation: 形成掩模图案的方法，形成微小图案的方法以及使用其形成半导体器件的方法，所述掩模图案的形成方法包括在基板上形成第一掩模图案; 在第一掩模图案上形成第一初步封盖层; 向第一初步封盖图案照射能量以形成与第一掩模图案离子键合的第二初步封盖层; 向第二初步封盖层施加酸以形成封盖层; 在所述封盖层之间形成第二掩模层，所述第二掩模层的溶解度低于所述封盖层的溶解度; 并去除覆盖层以形成第二掩模图案。

公开(公告)号：US20110027993A1

公开(公告)日：2011-02-03

申请号：US12794890

申请日：2010-06-07

Applicant: Seongho Moon ,  Yool Kang ,  HyoungHee Kim ,  Seokhwan Oh ,  So-Ra Han ,  Seongwoon Choi

Inventor： Seongho Moon ,  Yool Kang ,  HyoungHee Kim ,  Seokhwan Oh ,  So-Ra Han ,  Seongwoon Choi

IPC: H01L21/308

CPC classification number: H01L21/32139 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent.

Abstract translation: 提供了形成半导体器件的精细图案的方法。 该方法包括在基板上形成在平行于基板的表面的方向上彼此间隔开第一距离的多个初步第一掩模图案; 在所述基板上形成酸溶液层以覆盖所述多个初步第一掩模图案; 形成彼此间隔开大于第一距离的第二距离的多个第一掩模图案，其中上侧部分和第二部分被具有第一溶解度的酸性扩散区域包围; 通过除去酸溶液层暴露第一酸扩散区; 在所述酸扩散区之间形成第二掩模层，所述第二掩模层的第二溶解度低于所述第一溶解度; 以及分别通过所述溶剂除去所述酸扩散区而形成位于所述多个第一掩模图案之间的多个第二掩模图案。

公开(公告)号：US07678650B2

公开(公告)日：2010-03-16

申请号：US12453721

申请日：2009-05-20

Applicant: Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

Inventor： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC: H01L21/8247

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521

Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Abstract translation: 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US20090258473A1

公开(公告)日：2009-10-15

申请号：US12453721

申请日：2009-05-20

Applicant: Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

Inventor： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC: H01L21/762

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521

Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Abstract translation: 示例性实施例提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US20070077524A1

公开(公告)日：2007-04-05

申请号：US11529310

申请日：2006-09-29

Applicant: Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

Inventor： Cha-Won Koh ,  Yool Kang ,  Sang-Gyun Woo ,  Seok-Hwan Oh ,  Gi-Sung Yeo ,  Ji-Young Lee

IPC: G03F7/26

CPC classification number: G03F7/40 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

Abstract: Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法。 根据该方法，可以在衬底上形成第一掩模图案，并且可以在每个第一掩模图案的侧壁上形成第二掩模图案。 第三掩模图案可以填充在相邻的第二掩模图案之间形成的空间，并且可以去除第二掩模图案。 然后可以使用第一和第三掩模图案作为蚀刻掩模去除衬底的一部分。

公开(公告)号：US06280903B1

公开(公告)日：2001-08-28

申请号：US09618142

申请日：2000-07-17

Applicant: Yool Kang ,  Sang-Jun Choi ,  Dong-Won Jung ,  Chun-Geun Park ,  Young-Bum Koh

Inventor： Yool Kang ,  Sang-Jun Choi ,  Dong-Won Jung ,  Chun-Geun Park ,  Young-Bum Koh

IPC: G03C1492

CPC classification number: G03F7/039 ,  G03F7/0045

Abstract: Copolymers and terpolymers are used in chemically amplified resists. The terpolymers are of the formula: wherein R3 is selected from the group consisting of hydrogen and a C1 to C10 aliphatic hydrocarbon, wherein said aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof. R4 is selected from the group consisting of hydrogen and a C1 to C10 aliphatic hydrocarbon, wherein said aliphatic hydrocarbon contains substituents selected from the group consisting of hydrogen, hydroxy, carboxylic acid, carboxylic anhydride, and combinations thereof; R5 is selected from the group consisting of hydrogen and methyl; R6 is selected from the group consisting of t-butyl and tetrahydropyranyl; M and n are each integers; and wherein n/(m+n) ranges from about 0.1 to about 0.5.

Abstract translation: 共聚物和三元共聚物用于化学增强抗蚀剂。 三元共聚物具有下式：其中R 3选自氢和C 1至C 10脂族烃，其中所述脂族烃包含选自氢，羟基，羧酸，羧酸酐及其组合的取代基 。 R 4选自氢和C 1至C 10脂族烃，其中所述脂族烃包含选自氢，羟基，羧酸，羧酸酐及其组合的取代基; R5选自氢和甲基; R6选自叔丁基和四氢吡喃基; M和n分别是整数; 并且其中n /（m + n）为约0.1至约0.5。

公开(公告)号：US08431331B2

公开(公告)日：2013-04-30

申请号：US12267687

申请日：2008-11-10

Applicant: Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

Inventor： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

IPC: G03F7/40

CPC classification number: H01L21/027 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

Abstract translation: 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中，在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中，在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

公开(公告)号：US07560768B2

公开(公告)日：2009-07-14

申请号：US11594808

申请日：2006-11-09

Applicant: Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

Inventor： Cha-Won Koh ,  Byung-Hong Chung ,  Sang-Gyun Woo ,  Jeong-Lim Nam ,  Seok-Hwan Oh ,  Jai-Hyuk Song ,  Hyun Park ,  Yool Kang

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521

Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。 浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。 浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。 中间栅极图案和上部栅极图案之间的边界可以具有圆角。

公开(公告)号：US20080076070A1

公开(公告)日：2008-03-27

申请号：US11554324

申请日：2006-10-30

Applicant: Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

Inventor： Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

IPC: G03F7/00

CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

Abstract: A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.

Abstract translation: 通过在集成电路基板上形成牺牲图案，在集成电路基板上形成精细图案。 牺牲图案包括顶部和侧壁。 然后进行原子层沉积以在牺牲图案上沉积掩模材料层，包括在其顶部和侧壁上以及其间的集成电路基板上。 然后蚀刻原子层沉积的掩模材料层，以暴露其间的顶部和集成电路，使得掩模材料图案残留在侧壁上。 然后去除牺牲图案，然后通过保留的掩模材料图案蚀刻集成电路基板。

公开(公告)号：US06803176B2

公开(公告)日：2004-10-12

申请号：US10227067

申请日：2002-08-23

Applicant: Sang-jun Choi ,  Yool Kang ,  Joo-tae Moon ,  Jeong-hee Chung ,  Sang-gyun Woo

Inventor： Sang-jun Choi ,  Yool Kang ,  Joo-tae Moon ,  Jeong-hee Chung ,  Sang-gyun Woo

IPC: G03F740

CPC classification number: G03F7/40

Abstract: A method for forming a fine pattern in a semiconductor substrate, by coating a target layer to be etched on a semiconductor substrate with a resist composition including at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator. The free radical initiator is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound. A lithography process is performed on the resist compound layer to form a photoresist pattern. The resist compound layer having the photoresist pattern formed therein is heated to a temperature equal to or higher than the glass transition temperature of the at least one compound, and wherein a partial cross-linking reaction in the resist composition occurs.

Abstract translation: 一种在半导体衬底中形成精细图案的方法，其中通过用光刻工艺将包含至少一种能形成光致抗蚀剂图案的化合物的抗蚀剂组合物涂覆在半导体衬底上的待蚀刻靶材层和自由基引发剂。 自由基引发剂能够在等于或高于至少一种化合物的玻璃化转变温度的温度下被热处理分解。 在抗蚀剂化合物层上进行光刻工艺以形成光致抗蚀剂图案。 将其中形成有光致抗蚀剂图案的抗蚀剂化合物层加热到等于或高于至少一种化合物的玻璃化转变温度的温度，并且其中发生抗蚀剂组合物中的部分交联反应。