公开(公告)号：US07299311B1

公开(公告)日：2007-11-20

申请号：US11321508

申请日：2005-12-29

申请人： Chad M. Sepeda ,  Kelvin S. Vartti ,  Ross M. Weber

发明人： Chad M. Sepeda ,  Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F13/18

CPC分类号： G06F13/364

摘要： A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent to one or more arbitration ports, and the number of the coupled arbitration ports for the agent is the respective programmable weight. A selection module selects one of the arbitration ports in response to a priority ranking of the arbitration ports, and access to the resource group is granted to the agent that has the respective arbitration handshake signal that is selectively coupled by the programmable mapping module to the selected arbitration port. A ranking module provides the priority ranking of the arbitration ports and updates the priority ranking in response to the selection module selecting the selected arbitration port.

摘要翻译： 一种用于根据每个代理的相应可编程权重仲裁对代理之间的资源组的访问的系统和方法。 对于每个代理，可编程映射模块选择性地将代理的相应仲裁握手信号耦合到一个或多个仲裁端口，并且代理的耦合仲裁端口的数量是相应的可编程权重。 选择模块响应于仲裁端口的优先级排序选择一个仲裁端口，并且向具有相应的仲裁握手信号的代理授予对资源组的访问，所述仲裁握手信号由可编程映射模块选择性地耦合到所选择的 仲裁口岸 排序模块提供仲裁端口的优先级排序，并响应于选择模块选择所选仲裁端口而更新优先级排序。

公开(公告)号：US07533223B1

公开(公告)日：2009-05-12

申请号：US11784238

申请日：2007-04-06

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F13/1642

摘要： A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a linked list. Only the oldest pending one of these multiple requests is issued to the memory. When data is returned from the memory, the requests are processed in an order determined by the linked list. That is, the data is provided to a processor associated with the oldest request. Thereafter, the data is retrieved and provided to the processor associated with the next request, and so on. A request issued by the memory soliciting the return of the data to the memory may also be added to the linked list to be processed in the foregoing manner.

摘要翻译： 提供了一种系统和方法来跟踪数据处理系统内的存储器请求。 该系统包括一个请求跟踪电路，该电路被耦合以接收来自多个处理器的数据请求。 使用链表跟踪对同一内存地址的多个挂起请求。 只有这些多个请求中的最旧的等待一个发出到内存。 当从存储器返回数据时，以由链表确定的顺序处理请求。 也就是说，将数据提供给与最早请求相关联的处理器。 此后，数据被检索并提供给与下一请求相关联的处理器，等等。 由存储器发出的请求发出的请求也可以以上述方式被添加到链接列表中以被处理。

公开(公告)号：US07260677B1

公开(公告)日：2007-08-21

申请号：US10620515

申请日：2003-07-16

申请人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman

发明人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman

IPC分类号： G06F12/06

CPC分类号： G06F12/0817 ,  G06F12/084

摘要： A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in which this data is retrieved is determined by the state of programmable control indicators. In one mode of operation, a reference is made to the first memory to retrieve the data. If it is later determined from tag information stored by the first memory that the one or more additional memories must be accessed to fulfill the request, the necessary additional memory references are initiated. In another mode of operation, references to the one or more additional memories are initiated irrespective of whether these references are required. The operating mode may be selected to optimize system efficiency.

摘要翻译： 公开了一种存储器控制系统和方法。 在一个实施例中，第一存储器耦合到一个或多个附加存储器。 第一存储器通过从第一存储器和/或一个或多个附加存储器检索数据来接收对完成的数据的请求。 检索数据的方式由可编程控制指示灯的状态决定。 在一种操作模式中，引用第一存储器来检索数据。 如果随后由第一存储器存储的标签信息确定必须访问一个或多个附加存储器以满足请求，则启动必要的附加存储器引用。 在另一种操作模式中，无论是否需要这些引用，都会启动对一个或多个附加存储器的引用。 可以选择操作模式以优化系统效率。

公开(公告)号：US07496715B1

公开(公告)日：2009-02-24

申请号：US10620406

申请日：2003-07-16

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/601

摘要： A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control indicators. These indicators further control which data will be recorded by the tag logic. The indicators may select the sub-sets based on which type of memory request results in the return of data from the main memory to the cache, for example. Alternatively, or in addition, these indicators may specify the identity of a requester, a memory response type, or a storage mode to control the selection of the sub-sets of data stored within the cache and recorded by the tag logic. In one embodiment, data may be tracked by the cache tag logic but not stored within the cache itself.

摘要翻译： 公开了一种存储器控制系统和方法。 该系统包括高速缓存标签逻辑和耦合到主存储器的可选缓存。 如果可用，缓存保留存储在主存储器内的数据的子集。 该子集由可编程控制指示器选择。 这些指示器进一步控制标签逻辑将记录哪些数据。 指示符可以基于哪种类型的存储器请求导致将数据从主存储器返回到高速缓存而选择子集。 或者或另外，这些指示符可以指定请求者的身份，存储器响应类型或存储模式，以控制存储在高速缓存内并由标签逻辑记录的数据子集的选择。 在一个实施例中，数据可以被高速缓存标签逻辑跟踪，但是不存储在高速缓存本身中。

公开(公告)号：US07222222B1

公开(公告)日：2007-05-22

申请号：US10601030

申请日：2003-06-20

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F13/1642

摘要： A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a linked list. Only the oldest pending one of these multiple requests is issued to the memory. When data is returned from the memory, the requests are processed in an order determined by the linked list. That is, the data is provided to a processor associated with the oldest request. Thereafter, the data is retrieved and provided to the processor associated with the next request, and so on. A request issued by the memory soliciting the return of the data to the memory may also be added to the linked list to be processed in the foregoing manner.

摘要翻译： 提供了一种用于跟踪数据处理系统内的存储器请求的系统和方法。 该系统包括一个请求跟踪电路，该电路被耦合以接收来自多个处理器的数据请求。 使用链表跟踪对同一内存地址的多个挂起请求。 只有这些多个请求中的最旧的等待一个发出到内存。 当从存储器返回数据时，以由链表确定的顺序处理请求。 也就是说，将数据提供给与最早请求相关联的处理器。 此后，数据被检索并提供给与下一请求相关联的处理器，等等。 由存储器发出的请求发出的请求也可以以上述方式被添加到链接列表中以被处理。

公开(公告)号：US06973548B1

公开(公告)日：2005-12-06

申请号：US10600205

申请日：2003-06-20

申请人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman ,  Ronald G. Arnold

发明人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman ,  Ronald G. Arnold

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0828

摘要： A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

摘要翻译： 公开了一种双通道存储器系统和附带的一致性机制。 存储器包括请求和响应信道。 存储器通过响应信道向诸如指令处理器的请求者提供数据。 如果提供此数据用于更新目的，数据的其他只读副本必须无效。 在为更新目的提供数据之后可能发生这种无效，并且通过经由存储器请求或响应信道之一发出一个或多个无效请求来实现。 通过防止请求者将任何数据存储回存储器，直到所有可能与该数据直接或间接相关联的无效活动已经完成来维持内存一致性。

公开(公告)号：US20090172225A1

公开(公告)日：2009-07-02

申请号：US10926250

申请日：2004-08-25

申请人： Gregory B. Wiedenman ,  Nathan A. Eckel ,  Kelvin S. Vartti

发明人： Gregory B. Wiedenman ,  Nathan A. Eckel ,  Kelvin S. Vartti

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G06F13/4022

摘要： A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

摘要翻译： 一种多处理器系统，其中使用延迟相位响应方法，其允许延迟代理一旦获得系统接口总线的控制就中断总线事务的正常流量。 允许推迟剂向前看，以确定连续的延迟相循环是否在等待转移。 如果待处理，延迟代理将不会释放总线的控制，直到挂起的延迟阶段周期耗尽。 前瞻性功能允许快速返回更高优先级的延迟数据，同时最小化由与正常总线流量交错延迟相位周期引起的总线死区周期。

公开(公告)号：US06625698B2

公开(公告)日：2003-09-23

申请号：US09750637

申请日：2000-12-28

申请人： Kelvin S. Vartti

发明人： Kelvin S. Vartti

IPC分类号： G06F1200

CPC分类号： G06F12/0815

摘要： A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the target data segments during the time the targeted memory possesses ownership of the target data segments. A storage lock release signal is issued from the first requesting device to the targeted memory when exclusivity of the target data segments is no longer required at the first requesting device. In response, the storage lock at the targeted memory is released, thereby allowing other requesting devices to act on the target data segments.

公开(公告)号：US06993630B1

公开(公告)日：2006-01-31

申请号：US10255393

申请日：2002-09-26

申请人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin ,  Kelvin S. Vartti

发明人： James A. Williams ,  Robert H. Andrighetti ,  Conrad S. Shimada ,  Donald C. Englin ,  Kelvin S. Vartti

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.

摘要翻译： 公开了一种用于预取数据信号的系统和方法。 根据本发明的一个方面，指令处理器（IP）产生访问高速缓存内的数据信号的请求。 将预定的请求提供给预取控制逻辑，其确定数据信号是否在高速缓存内可用。 如果不是，数据信号从数据处理系统中的另一个存储器检索，并被存储到高速缓存。 根据一个方面，可以可编程地选择生成预取请求的速率以匹配将相关联的数据信号请求提供给高速缓存的速率。 在另一个实施例中，预取控制逻辑接收信息以使用将预取控制逻辑耦合到IP的专用接口来生成预取请求。

公开(公告)号：US06857049B1

公开(公告)日：2005-02-15

申请号：US09651488

申请日：2000-08-30

申请人： Donald C. Englin ,  Kelvin S. Vartti ,  James L. Federici

发明人： Donald C. Englin ,  Kelvin S. Vartti ,  James L. Federici

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804

摘要： A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache memory is a store-in memory. Therefore, when data is to be deleted from the second level cache memory, a determination is made whether the data has been modified by the processor. If the data has been modified, the data must be rewritten to lower level memory. To free the second level cache memory for storage of the newly requested data, the data to be flush is loaded into a flush buffer for storage during the rewriting process.

摘要翻译： 一种用于提高采用多级高速缓冲存储器系统的数据处理系统的效率的方法和装置。 通过管理从第二级高速缓冲存储器刷新旧数据的过程导致效率。 在本发明中，第二级高速缓冲存储器是存储存储器。 因此，当要从第二级高速缓冲存储器中删除数据时，确定数据是否已被处理器修改。 如果数据被修改，则数据必须重新写入较低级别的内存。 要释放用于存储新请求的数据的第二级高速缓冲存储器，要刷新的数据将在重写过程中加载到刷新缓冲区中以进行存储。