公开(公告)号：US06221772B1

公开(公告)日：2001-04-24

申请号：US09352747

申请日：1999-07-14

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Wei-Che Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Wei-Che Huang

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  C11D7/02 ,  C11D11/0047 ,  G03F7/427 ,  H01L21/31138 ,  H01L21/76814

摘要： The present invention provides a method of in-situ cleaning polymers from holes on a semiconductor wafer and in-situ removing the silicon nitride layer. The semiconductor wafer comprising a substrate, a silicon nitride (Si3N4) layer on the substrate, a silicon oxide (SiO2) layer on the silicon nitride layer, and a photo-resist layer on the silicon oxide layer. The silicon oxide layer and the photo-resist layer have a hole extending down to the silicon nitride layer. The hole contains polymer left after etching of the silicon oxide layer. The method comprises performing a in-situ plasma ashing process by injecting oxygen (O2) and argon (Ar) to completely remove the photo-resist layer and the polymer remaining within the hole. Subsequently, the silicon nitride layer was removed in the same chamber. The flow rate of O2 is maintained between 50˜2000 sccm (standard cubic centimeter per minute) and the flow rate of Ar is maintained between 50˜500 sccm.

摘要翻译： 本发明提供了一种从半导体晶片上的孔中原位清洗聚合物并原位去除氮化硅层的方法。 包括衬底，衬底上的氮化硅（Si 3 N 4）层，氮化硅层上的氧化硅（SiO 2）层和氧化硅层上的光致抗蚀剂层的半导体晶片。 氧化硅层和光致抗蚀剂层具有向下延伸到氮化硅层的孔。 该孔含有在氧化硅层蚀刻后残留的聚合物。 该方法包括通过注入氧（O 2）和氩（Ar）进行原位等离子体灰化处理，以完全除去光刻胶层和留在孔内的聚合物。 随后，在相同的室中除去氮化硅层。 O2的流量保持在50〜2000sccm（标准立方厘米每分钟）之间，Ar的流量保持在50〜500sccm之间。

公开(公告)号：US6147007A

公开(公告)日：2000-11-14

申请号：US330597

申请日：1999-06-11

申请人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814

摘要： The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.

摘要翻译： 本发明涉及在半导体晶片上形成接触孔的方法。 半导体晶片按照升序包括衬底，氮化硅层，氧化硅层和光致抗蚀剂层。 光致抗蚀剂层中有一个孔。 该方法包括：（1）沿向下的方向进行第一各向异性蚀刻处理，以将氧化硅层下面的氮化硅层的表面去除，形成凹部; （2）进行原位等离子体清洗工艺以完全除去残留在凹部底部的聚合物材料; （3）在向下的方向上进行原位第二各向异性蚀刻工艺，以将氮化硅层从凹槽的底部向下移动到衬底的表面，以形成接触孔; （4）进行另一原位清洗处理以完全除去留在接触孔底部的聚合物材料。

公开(公告)号：US06352938B2

公开(公告)日：2002-03-05

申请号：US09457561

申请日：1999-12-09

申请人： Tong-Yu Chen ,  Hsi-Ta Chuang ,  Chan-Lon Yang

发明人： Tong-Yu Chen ,  Hsi-Ta Chuang ,  Chan-Lon Yang

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879

摘要： A method of manufacturing metallic interconnects. A substrate has a copper line formed therein. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to form a trench and a contact opening that exposes a portion of the copper line, wherein the contact opening is under the trench. At a low temperature and using a plasma derived from a gaseous mixture N2H2 (H2:4%)/O2, the photoresist layer is removed. Any copper oxide layer formed on the copper line in the process of removing photoresist material is reduced back to copper using gaseous N2H2 (H2:4%). A barrier layer conformal to the trench and the contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening. Using the first copper layer as a seeding layer, a copper or a copperless electroplating is carried out so that a second copper layer is grown anisotropically over the first copper layer.

摘要翻译： 一种制造金属互连的方法。 基板上形成有铜线。 在衬底和铜线之上形成金属间介电层。 在金属间介电层上形成图案化的光致抗蚀剂层。 蚀刻金属间电介质层以形成暴露铜线的一部分的沟槽和接触开口，其中接触开口在沟槽下方。 在低温下并使用来自气态混合物N 2 H 2（H 2：4％）/ O 2）的等离子体，除去光致抗蚀剂层。 在除去光致抗蚀剂材料的工艺中在铜线上形成的任何铜氧化物层都使用气态N 2 H 2（H 2：4％）还原成铜。 形成与沟槽一致的阻挡层和形成接触开口轮廓。 沉积铜以在沟槽和接触开口上形成共形的第一铜层。 使用第一铜层作为接种层，进行铜或无铜电镀，使得第二铜层在第一铜层上各向异性地生长。

公开(公告)号：US5994233A

公开(公告)日：1999-11-30

申请号：US172507

申请日：1998-10-14

申请人： Tong-Yu Chen ,  Chan-Lon Yang ,  Tsu-An Lin

发明人： Tong-Yu Chen ,  Chan-Lon Yang ,  Tsu-An Lin

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/31116

摘要： An oxide etching method using low-medium density plasma includes a first etching step to pre-etch the oxide layer with low etching selectivity etchant to pre-form a contact opening and a monitoring opening. The low etching selectivity etchant can also etch the photoresist layer and the photoresist reaction residue. Then, a second etching with high etching selectivity on the oxide is performed to completely form the contact opening with a SAC property and the monitoring opening. The openings expose the substrate.

摘要翻译： 使用低介质密度等离子体的氧化物蚀刻方法包括用低蚀刻选择性蚀刻剂预蚀刻氧化物层以预先形成接触开口和监测开口的第一蚀刻步骤。 低蚀刻选择性蚀刻剂也可以蚀刻光致抗蚀剂层和光致抗蚀剂反应残余物。 然后，执行对氧化物具有高蚀刻选择性的第二蚀刻，以完全形成具有SAC特性和监测开口的接触开口。 开口露出基板。

公开(公告)号：US6083845A

公开(公告)日：2000-07-04

申请号：US255678

申请日：1999-02-23

申请人： Chan-Lon Yang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76816

摘要： An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

摘要翻译： 在高密度等离子体蚀刻系统中使用蚀刻方法来蚀刻氧化硅介电层以形成不同深度的开口。 该方法使用C4H8，CH2F2和Ar的混合物作为蚀刻气体源来蚀刻氧化硅介电层，形成第一深度的多个开口。 使用C4H8，CO和Ar的混合物作为蚀刻气体源来蚀刻由第一开口暴露的氧化硅介电层，使得开口加深到第二深度。 使用C4H8，CH2F2，CO和Ar的混合物作为蚀刻气体源，蚀刻由开口暴露的氧化硅介电层，使得开口加深到第三深度和第四深度。

公开(公告)号：US06528428B1

公开(公告)日：2003-03-04

申请号：US09638416

申请日：2000-08-14

申请人： Tong-Yu Chen ,  Chan-Lon Yang

发明人： Tong-Yu Chen ,  Chan-Lon Yang

IPC分类号： H01L21311

CPC分类号： H01L21/76808 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene structure. A first dielectric layer, an etching stop layer, a second dielectric layer and a hard mask layer are sequentially formed over a substrate. Photolithographic and etching operations are conducted to remove a portion of the hard mask layer, the second dielectric layer, the etching stop layer and the first dielectric layer so that a via opening is formed. A conformal dielectric layer is formed on the surface of the hard mask layer and the interior surface of the via opening. An anisotropic etching operation is carried out to form spacers on the sidewalls of the via opening. A patterned photoresist layer is formed over the hard mask layer. Using the patterned photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Chemical-mechanical polishing is conducted to remove excess conductive material above the hard mask layer.

摘要翻译： 形成双镶嵌结构的方法。 在衬底上顺序地形成第一电介质层，蚀刻停止层，第二电介质层和硬掩模层。 进行光刻和蚀刻操作以去除硬掩模层，第二介电层，蚀刻停止层和第一介电层的一部分，从而形成通孔。 在硬掩模层的表面和通孔开口的内表面上形成保形介电层。 进行各向异性蚀刻操作以在通孔开口的侧壁上形成间隔物。 在硬掩模层上形成图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为掩模，去除第二介电层的一部分以形成沟槽。 去除图案化的光致抗蚀剂层。 导电材料沉积在衬底上以填充通孔和沟槽。 进行化学机械抛光以去除硬掩模层上方的过量导电材料。

公开(公告)号：US06426298B1

公开(公告)日：2002-07-30

申请号：US09637811

申请日：2000-08-11

申请人： Tong-Yu Chen ,  Chan-Lon Yang

发明人： Tong-Yu Chen ,  Chan-Lon Yang

IPC分类号： H01L21311

CPC分类号： H01L21/76835 ,  H01L21/76808

摘要： A substrate is provided. A first dielectric is formed over the substrate, and an etching stop layer and a second dielectric are formed in turn on the first dielectric by deposition. An anti-reflection layer is formed over the second dielectric. Then, a photo-resist layer is formed and defined over the anti-reflection layer. A gap-filling material is filled on the second dielectric and into the via hole. Subsequently, the gap-filling material is etched back and is turned on the end point and the long over etch is applied to make sure the photo-resist thickness is below middle stop layer. If the first dielectric reacts with the photo-resist plug in the via hole, the bottom anti-reflection coating or thin oxide are used as a barrier before the trench photo-resist is patterned. If the first dielectric does not react with the photo-resist plug in the via hole, the trench photo-resist is patterned directly. Then, the trench etch is performed.

摘要翻译： 提供基板。 在衬底上形成第一电介质，并且通过沉积在第一电介质上依次形成蚀刻停止层和第二电介质。 在第二电介质上形成防反射层。 然后，在抗反射层上形成并限定光致抗蚀剂层。 间隙填充材料填充在第二电介质上并进入通孔。 随后，将间隙填充材料回蚀刻并在端点上打开，并施加长时间的蚀刻以确保光刻胶厚度低于中间停止层。 如果第一电介质与通孔中的光致抗蚀剂插塞反应，则在将沟槽光致抗蚀剂图案化之前，将底部抗反射涂层或薄氧化物用作屏障。 如果第一电介质不与通孔中的光刻胶塞反应，则直接对沟槽光刻胶进行图案化。 然后，进行沟槽蚀刻。

公开(公告)号：US06307174B1

公开(公告)日：2001-10-23

申请号：US09533036

申请日：2000-03-22

申请人： Chan-Lon Yang ,  Michael W C Huang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Michael W C Huang ,  Tong-Yu Chen

IPC分类号： B23K1000

CPC分类号： B23K10/00

摘要： A method for high-density plasma etching. A substrate is provided. A material layer is formed on the substrate. A patterned photo-resist layer is formed on the oxide layer. The material layer is patterned by the high-density plasma etching, simultaneously, a formation of a barrier layer over the substrate with the patterning process is suppressed and nitrogen gas generated in the patterned photo-resist layer is reduced.

摘要翻译： 一种用于高密度等离子体蚀刻的方法。 提供基板。 在基板上形成材料层。 在氧化物层上形成图案化的光刻胶层。 通过高密度等离子体蚀刻来对材料层进行构图，同时，通过图案化工艺在衬底上形成阻挡层，并且在图案化光刻胶层中产生的氮气减少。

公开(公告)号：US6139702A

公开(公告)日：2000-10-31

申请号：US263386

申请日：1999-03-05

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

IPC分类号： C23C14/06 ,  C23C14/34 ,  H01L21/311 ,  G23C14/34

CPC分类号： C23C14/0682 ,  C23C14/3457 ,  H01L21/31116

摘要： A seasoning process for an etcher which is performed before etching a dielectric layer to expose a metal silicide layer. The seasoning process includes the first plasma sputtering process and the second plasma sputtering process. A wafer containing the metal silicide layer thereon is placed in the etcher with an etchant and the first plasma sputtering process is performed. Several silicon wafers are successively placed in the etcher to perform the second plasma sputtering process.

摘要翻译： 在蚀刻介电层以暴露金属硅化物层之前执行的蚀刻器的调味过程。 调味过程包括第一等离子体溅射工艺和第二等离子体溅射工艺。 将含有其上的金属硅化物层的晶片用蚀刻剂放置在蚀刻器中，并且执行第一等离子体溅射工艺。 将几个硅晶片依次放置在蚀刻器中以进行第二等离子体溅射工艺。

公开(公告)号：US6010968A

公开(公告)日：2000-01-04

申请号：US220541

申请日：1998-12-24

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

IPC分类号： H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116

摘要： A multilevel contact etching method to form a contact opening is provided. The method contains using an inductively coupled plasma (ICP) etcher to produce a high plasma density condition. The plasma gas etchant is composed of C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 /CO/Ar with a ratio of 3:4:12:80 so that silicon nitride can be selectively etched while the silicon and silicide are not etched. Each content ratio of the plasma gas etchant allows a variance of about 20%. Wall temperature of the ICP etcher is about 100.degree. C.-300.degree. C. A cooling system for a wafer pad is about -20.degree. C.-20.degree. C. Chamber pressure is about 5-100 mtorr. Bias power on the wafer pad is about 1000 W-3000 W. Source power of an inductance coil is about 500 W-3000 W.

摘要翻译： 提供了形成接触开口的多层接触蚀刻方法。 该方法包括使用电感耦合等离子体（ICP）蚀刻器来产生高等离子体密度条件。 等离子体气体蚀刻剂由比例为3：4：12：80的C4F8 / CH2F2 / CO / Ar组成，以便在不蚀刻硅和硅化物的情况下，可以选择性地蚀刻氮化硅。 等离子体气体蚀刻剂的每个含量比允许约20％的变化。 ICP蚀刻器的壁温为约100℃-300℃。晶片垫的冷却系统为约-20℃-20℃。室压力为约5-100mtorr。 晶片垫上的偏置功率约为1000W-3000W。电感线圈的功率为约500W-3000W。