公开(公告)号：US09105590B2

公开(公告)日：2015-08-11

申请号：US13206523

申请日：2011-08-10

申请人： Tong-Yu Chen

发明人： Tong-Yu Chen

IPC分类号： H01L29/06 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76838

摘要： A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.

摘要翻译： 在本发明中提供半导体结构。 半导体结构包括基板，第一材料层和第二材料层。 在衬底上限定沟槽区域。 沟槽区域包括两个分开的第一区域和第二区域，其中第二区域与两个第一区域相邻并且在两个第一区域之间。 第一材料层设置在沟槽区域外的衬底上。 第二材料层设置在第二区域中并与第一材料层平齐。

公开(公告)号：US09012975B2

公开(公告)日：2015-04-21

申请号：US13517759

申请日：2012-06-14

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/792

摘要： A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

摘要翻译： 提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。 翅片凸块设置在基板上。 绝缘层设置在基板上并且位于散热片凸块的两侧。 电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。 电荷捕获结构的横截面为L形。 栅极结构覆盖鳍片凸起和电荷俘获结构。

公开(公告)号：US08946078B2

公开(公告)日：2015-02-03

申请号：US13426624

申请日：2012-03-22

申请人： Tong-Yu Chen ,  Chih-Jung Wang

发明人： Tong-Yu Chen ,  Chih-Jung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

摘要翻译： 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

公开(公告)号：US20130154028A1

公开(公告)日：2013-06-20

申请号：US13326429

申请日：2011-12-15

申请人： Chih-Jung WANG ,  Tong-Yu CHEN

发明人： Chih-Jung WANG ,  Tong-Yu CHEN

IPC分类号： H01L27/088

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

摘要翻译： 提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。 翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。 第一掺杂浓度大于第二掺杂浓度。 阻挡区域具有高度。 通道区域被配置在阻塞区域之上。 栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。 栅极绝缘层设置在栅极条和鳍状半导体结构之间。

公开(公告)号：US06361929B1

公开(公告)日：2002-03-26

申请号：US09373755

申请日：1999-08-13

申请人： Hsein-Ta Chung ,  Yi-Yu Hsu ,  Tong-Yu Chen ,  Tri-Rung Yew

发明人： Hsein-Ta Chung ,  Yi-Yu Hsu ,  Tong-Yu Chen ,  Tri-Rung Yew

IPC分类号： G03F736

CPC分类号： G03F7/427 ,  G03F7/42

摘要： The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.

摘要翻译： 本发明涉及从半导体晶片去除光致抗蚀剂层的方法。 半导体晶片包括金属间介电层（IMD）和位于IMD上的光致抗蚀剂层。 该方法包括通过将含氮气体注入无氧环境并利用等离子体反应去除大部分光致抗蚀剂层进行干洗处理，并进行湿式清洗处理以完全除去光致抗蚀剂层 。

公开(公告)号：US6083845A

公开(公告)日：2000-07-04

申请号：US255678

申请日：1999-02-23

申请人： Chan-Lon Yang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76816

摘要： An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

摘要翻译： 在高密度等离子体蚀刻系统中使用蚀刻方法来蚀刻氧化硅介电层以形成不同深度的开口。 该方法使用C4H8，CH2F2和Ar的混合物作为蚀刻气体源来蚀刻氧化硅介电层，形成第一深度的多个开口。 使用C4H8，CO和Ar的混合物作为蚀刻气体源来蚀刻由第一开口暴露的氧化硅介电层，使得开口加深到第二深度。 使用C4H8，CH2F2，CO和Ar的混合物作为蚀刻气体源，蚀刻由开口暴露的氧化硅介电层，使得开口加深到第三深度和第四深度。

公开(公告)号：US08803247B2

公开(公告)日：2014-08-12

申请号：US13326429

申请日：2011-12-15

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L27/148 ,  H01L29/66 ,  H01L29/00 ,  H01L27/088 ,  H01L21/339 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/337 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

摘要翻译： 提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。 翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。 第一掺杂浓度大于第二掺杂浓度。 阻挡区域具有高度。 通道区域被配置在阻塞区域之上。 栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。 栅极绝缘层设置在栅极条和鳍状半导体结构之间。

公开(公告)号：US07319074B2

公开(公告)日：2008-01-15

申请号：US11160178

申请日：2005-06-13

申请人： Pei-Yu Chou ,  Tong-Yu Chen

发明人： Pei-Yu Chou ,  Tong-Yu Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/31138 ,  H01L21/32137

摘要： The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.

摘要翻译： 本发明提供了一种限定多晶硅图案的方法。 该方法在衬底上形成多晶硅层，并在多晶硅层上形成图案化掩模。 然后，进行第一蚀刻处理以去除未被掩模覆盖的多晶硅层的一部分，从而在多晶硅层中形成多个空腔。 执行条带处理以利用除O 2以外的气体剥离掩模。 最后，执行第二蚀刻工艺以去除多晶硅层的一部分，从而将多个空腔向下延伸到衬底的表面。

公开(公告)号：US06972259B2

公开(公告)日：2005-12-06

申请号：US10291911

申请日：2002-11-13

申请人： Chih-Jung Wang ,  Tong-Yu Chen

发明人： Chih-Jung Wang ,  Tong-Yu Chen

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76813

摘要： The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

公开(公告)号：US06352938B2

公开(公告)日：2002-03-05

申请号：US09457561

申请日：1999-12-09

申请人： Tong-Yu Chen ,  Hsi-Ta Chuang ,  Chan-Lon Yang

发明人： Tong-Yu Chen ,  Hsi-Ta Chuang ,  Chan-Lon Yang

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879

摘要： A method of manufacturing metallic interconnects. A substrate has a copper line formed therein. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to form a trench and a contact opening that exposes a portion of the copper line, wherein the contact opening is under the trench. At a low temperature and using a plasma derived from a gaseous mixture N2H2 (H2:4%)/O2, the photoresist layer is removed. Any copper oxide layer formed on the copper line in the process of removing photoresist material is reduced back to copper using gaseous N2H2 (H2:4%). A barrier layer conformal to the trench and the contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening. Using the first copper layer as a seeding layer, a copper or a copperless electroplating is carried out so that a second copper layer is grown anisotropically over the first copper layer.

摘要翻译： 一种制造金属互连的方法。 基板上形成有铜线。 在衬底和铜线之上形成金属间介电层。 在金属间介电层上形成图案化的光致抗蚀剂层。 蚀刻金属间电介质层以形成暴露铜线的一部分的沟槽和接触开口，其中接触开口在沟槽下方。 在低温下并使用来自气态混合物N 2 H 2（H 2：4％）/ O 2）的等离子体，除去光致抗蚀剂层。 在除去光致抗蚀剂材料的工艺中在铜线上形成的任何铜氧化物层都使用气态N 2 H 2（H 2：4％）还原成铜。 形成与沟槽一致的阻挡层和形成接触开口轮廓。 沉积铜以在沟槽和接触开口上形成共形的第一铜层。 使用第一铜层作为接种层，进行铜或无铜电镀，使得第二铜层在第一铜层上各向异性地生长。